Lines Matching +full:ssc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
19 #include <dt-bindings/phy/phy.h>
79 u8 mode; member
98 ret = regmap_read(base, reg->offset, &orig); in param_read()
102 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
103 tmp = (orig & mask) >> reg->bitstart; in param_read()
113 tmp = en ? reg->enable : reg->disable; in param_write()
114 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
115 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
117 return regmap_write(base, reg->offset, val); in param_write()
122 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
125 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
126 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
128 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
129 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
139 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
140 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
142 dev_err(priv->dev, "failed to init phy for pcie\n"); in rockchip_combphy_pcie_init()
147 if (priv->cfg->force_det_out) { in rockchip_combphy_pcie_init()
148 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
150 writel(val, priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
158 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; in rockchip_combphy_usb3_init()
161 if (device_property_present(priv->dev, "rockchip,dis-u3otg0-port")) { in rockchip_combphy_usb3_init()
162 ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, in rockchip_combphy_usb3_init()
165 } else if (device_property_present(priv->dev, "rockchip,dis-u3otg1-port")) { in rockchip_combphy_usb3_init()
166 ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, in rockchip_combphy_usb3_init()
171 if (priv->cfg->combphy_cfg) { in rockchip_combphy_usb3_init()
172 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_usb3_init()
174 dev_err(priv->dev, "failed to init phy for usb3\n"); in rockchip_combphy_usb3_init()
186 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sata_init()
187 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sata_init()
189 dev_err(priv->dev, "failed to init phy for sata\n"); in rockchip_combphy_sata_init()
201 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sgmii_init()
202 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sgmii_init()
204 dev_err(priv->dev, "failed to init phy for sgmii\n"); in rockchip_combphy_sgmii_init()
214 switch (priv->mode) { in rockchip_combphy_set_mode()
228 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_set_mode()
229 return -EINVAL; in rockchip_combphy_set_mode()
238 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
242 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
244 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
252 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
256 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_init()
257 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_init()
259 if (priv->mode == PHY_TYPE_USB3) { in rockchip_combphy_init()
262 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
265 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
271 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
279 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_exit()
281 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_exit()
282 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); in rockchip_combphy_exit()
284 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
285 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
301 if (args->args_count != 1) { in rockchip_combphy_xlate()
303 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
306 if (priv->mode != PHY_NONE && priv->mode != args->args[0]) in rockchip_combphy_xlate()
308 args->args[0], priv->mode); in rockchip_combphy_xlate()
310 priv->mode = args->args[0]; in rockchip_combphy_xlate()
312 return priv->phy; in rockchip_combphy_xlate()
318 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; in rockchip_combphy_parse_dt()
322 ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); in rockchip_combphy_parse_dt()
323 if (ret == -EPROBE_DEFER) in rockchip_combphy_parse_dt()
324 return -EPROBE_DEFER; in rockchip_combphy_parse_dt()
326 priv->num_clks = 0; in rockchip_combphy_parse_dt()
328 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_combphy_parse_dt()
329 "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
330 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
331 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
332 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
335 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_combphy_parse_dt()
336 "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
337 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
338 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
339 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
342 if (device_property_present(dev, "rockchip,dis-u3otg0-port")) in rockchip_combphy_parse_dt()
343 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, in rockchip_combphy_parse_dt()
345 else if (device_property_present(dev, "rockchip,dis-u3otg1-port")) in rockchip_combphy_parse_dt()
346 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, in rockchip_combphy_parse_dt()
349 if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) && in rockchip_combphy_parse_dt()
351 param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, in rockchip_combphy_parse_dt()
354 if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", in rockchip_combphy_parse_dt()
356 regmap_write(priv->pipe_grf, vals[0], in rockchip_combphy_parse_dt()
359 priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb"); in rockchip_combphy_parse_dt()
360 if (IS_ERR(priv->apb_rst)) { in rockchip_combphy_parse_dt()
361 ret = PTR_ERR(priv->apb_rst); in rockchip_combphy_parse_dt()
363 if (ret != -EPROBE_DEFER) in rockchip_combphy_parse_dt()
369 priv->phy_rst = devm_reset_control_get_optional(dev, "combphy"); in rockchip_combphy_parse_dt()
370 if (IS_ERR(priv->phy_rst)) { in rockchip_combphy_parse_dt()
371 ret = PTR_ERR(priv->phy_rst); in rockchip_combphy_parse_dt()
373 if (ret != -EPROBE_DEFER) in rockchip_combphy_parse_dt()
379 return reset_control_assert(priv->phy_rst); in rockchip_combphy_parse_dt()
385 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
394 return -EINVAL; in rockchip_combphy_probe()
399 return -ENOMEM; in rockchip_combphy_probe()
402 priv->mmio = devm_ioremap_resource(dev, res); in rockchip_combphy_probe()
403 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
404 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
408 priv->num_clks = phy_cfg->num_clks; in rockchip_combphy_probe()
410 priv->clks = devm_kmemdup(dev, phy_cfg->clks, in rockchip_combphy_probe()
411 phy_cfg->num_clks * sizeof(struct clk_bulk_data), in rockchip_combphy_probe()
414 if (!priv->clks) in rockchip_combphy_probe()
415 return -ENOMEM; in rockchip_combphy_probe()
417 priv->dev = dev; in rockchip_combphy_probe()
418 priv->mode = PHY_NONE; in rockchip_combphy_probe()
419 priv->cfg = phy_cfg; in rockchip_combphy_probe()
425 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); in rockchip_combphy_probe()
426 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
428 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
432 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
441 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg()
448 for (i = 0; i < priv->num_clks; i++) { in rk3528_combphy_cfg()
449 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3528_combphy_cfg()
450 refclk = priv->clks[i].clk; in rk3528_combphy_cfg()
456 dev_err(priv->dev, "No refclk found\n"); in rk3528_combphy_cfg()
457 return -EINVAL; in rk3528_combphy_cfg()
460 switch (priv->mode) { in rk3528_combphy_cfg()
462 /* Set SSC downward spread spectrum */ in rk3528_combphy_cfg()
463 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
466 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
468 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
469 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
470 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
471 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
474 /* Set SSC downward spread spectrum */ in rk3528_combphy_cfg()
475 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
478 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
481 val = readl(priv->mmio + 0x200); in rk3528_combphy_cfg()
484 writel(val, priv->mmio + 0x200); in rk3528_combphy_cfg()
487 val = readl(priv->mmio + 0x20c); in rk3528_combphy_cfg()
490 writel(val, priv->mmio + 0x20c); in rk3528_combphy_cfg()
492 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
493 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
494 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
497 dev_err(priv->dev, "incompatible PHY type\n"); in rk3528_combphy_cfg()
498 return -EINVAL; in rk3528_combphy_cfg()
505 param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3528_combphy_cfg()
506 if (priv->mode == PHY_TYPE_USB3) { in rk3528_combphy_cfg()
508 val = readl(priv->mmio + 0x100); in rk3528_combphy_cfg()
511 writel(val, priv->mmio + 0x100); in rk3528_combphy_cfg()
512 } else if (priv->mode == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
514 val = readl(priv->mmio + 0x218); in rk3528_combphy_cfg()
516 writel(val, priv->mmio + 0x218); in rk3528_combphy_cfg()
520 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
521 if (priv->mode == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
523 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
526 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
530 writel(val, priv->mmio + 0x108); in rk3528_combphy_cfg()
534 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3528_combphy_cfg()
535 return -EINVAL; in rk3528_combphy_cfg()
542 /* pipe-phy-grf */
559 /* pipe-grf */
578 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg()
585 for (i = 0; i < priv->num_clks; i++) { in rk3562_combphy_cfg()
586 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3562_combphy_cfg()
587 refclk = priv->clks[i].clk; in rk3562_combphy_cfg()
593 dev_err(priv->dev, "No refclk found\n"); in rk3562_combphy_cfg()
594 return -EINVAL; in rk3562_combphy_cfg()
597 switch (priv->mode) { in rk3562_combphy_cfg()
599 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
600 val = readl(priv->mmio + (0x1f << 2)); in rk3562_combphy_cfg()
603 writel(val, priv->mmio + 0x7c); in rk3562_combphy_cfg()
605 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
606 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
607 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
608 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
611 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
612 val = readl(priv->mmio + (0x1f << 2)); in rk3562_combphy_cfg()
615 writel(val, priv->mmio + 0x7c); in rk3562_combphy_cfg()
618 val = readl(priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
621 writel(val, priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
624 val = readl(priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
627 writel(val, priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
630 writel(0x4, priv->mmio + (0xb << 2)); in rk3562_combphy_cfg()
633 val = readl(priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
636 writel(val, priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
639 writel(0x32, priv->mmio + (0x11 << 2)); in rk3562_combphy_cfg()
642 writel(0xf0, priv->mmio + (0xa << 2)); in rk3562_combphy_cfg()
645 writel(0x0e, priv->mmio + (0x14 << 2)); in rk3562_combphy_cfg()
647 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
648 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
649 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
650 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
653 dev_err(priv->dev, "incompatible PHY type\n"); in rk3562_combphy_cfg()
654 return -EINVAL; in rk3562_combphy_cfg()
661 if (priv->mode == PHY_TYPE_USB3) { in rk3562_combphy_cfg()
663 val = readl(priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
666 writel(val, priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
668 val = readl(priv->mmio + (0x0f << 2)); in rk3562_combphy_cfg()
671 writel(val, priv->mmio + (0x0f << 2)); in rk3562_combphy_cfg()
675 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3562_combphy_cfg()
678 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
679 if (priv->mode == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
681 val = readl(priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
684 writel(val, priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
687 writel(0x4, priv->mmio + (0xb << 2)); in rk3562_combphy_cfg()
689 val = readl(priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
692 writel(val, priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
694 writel(0x32, priv->mmio + (0x11 << 2)); in rk3562_combphy_cfg()
695 writel(0xf0, priv->mmio + (0xa << 2)); in rk3562_combphy_cfg()
698 val = readl(priv->mmio + (0xd << 2)); in rk3562_combphy_cfg()
701 writel(val, priv->mmio + (0xd << 2)); in rk3562_combphy_cfg()
705 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3562_combphy_cfg()
706 return -EINVAL; in rk3562_combphy_cfg()
709 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3562_combphy_cfg()
710 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3562_combphy_cfg()
711 if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { in rk3562_combphy_cfg()
712 val = readl(priv->mmio + (0xc << 2)); in rk3562_combphy_cfg()
714 writel(val, priv->mmio + (0xc << 2)); in rk3562_combphy_cfg()
716 val = readl(priv->mmio + (0xd << 2)); in rk3562_combphy_cfg()
718 writel(val, priv->mmio + (0xd << 2)); in rk3562_combphy_cfg()
722 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3562_combphy_cfg()
723 val = readl(priv->mmio + (0x7 << 2)); in rk3562_combphy_cfg()
725 writel(val, priv->mmio + (0x7 << 2)); in rk3562_combphy_cfg()
732 /* pipe-phy-grf */
753 /* peri-grf */
773 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
780 for (i = 0; i < priv->num_clks; i++) { in rk3568_combphy_cfg()
781 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3568_combphy_cfg()
782 refclk = priv->clks[i].clk; in rk3568_combphy_cfg()
788 dev_err(priv->dev, "No refclk found\n"); in rk3568_combphy_cfg()
789 return -EINVAL; in rk3568_combphy_cfg()
792 switch (priv->mode) { in rk3568_combphy_cfg()
794 /* Set SSC downward spread spectrum */ in rk3568_combphy_cfg()
795 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
798 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
800 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
801 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
802 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
803 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
806 /* Set SSC downward spread spectrum */ in rk3568_combphy_cfg()
807 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
810 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
813 val = readl(priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
816 writel(val, priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
819 val = readl(priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
822 writel(val, priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
825 writel(0x4, priv->mmio + (0xb << 2)); in rk3568_combphy_cfg()
828 val = readl(priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
831 writel(val, priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
834 writel(0x32, priv->mmio + (0x11 << 2)); in rk3568_combphy_cfg()
837 writel(0xf0, priv->mmio + (0xa << 2)); in rk3568_combphy_cfg()
840 writel(0x0e, priv->mmio + (0x14 << 2)); in rk3568_combphy_cfg()
842 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
843 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
844 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
845 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
848 writel(0x41, priv->mmio + 0x38); in rk3568_combphy_cfg()
849 writel(0x8F, priv->mmio + 0x18); in rk3568_combphy_cfg()
850 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
851 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
852 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
853 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
854 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
857 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
858 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
859 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
860 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
863 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
864 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
865 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
866 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
867 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
870 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
871 return -EINVAL; in rk3568_combphy_cfg()
878 if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
880 val = readl(priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
883 writel(val, priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
885 val = readl(priv->mmio + (0x0f << 2)); in rk3568_combphy_cfg()
888 writel(val, priv->mmio + (0x0f << 2)); in rk3568_combphy_cfg()
892 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
895 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
896 if (priv->mode == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
898 val = readl(priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
901 writel(val, priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
904 writel(0x4, priv->mmio + (0xb << 2)); in rk3568_combphy_cfg()
906 val = readl(priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
909 writel(val, priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
911 writel(0x32, priv->mmio + (0x11 << 2)); in rk3568_combphy_cfg()
912 writel(0xf0, priv->mmio + (0xa << 2)); in rk3568_combphy_cfg()
913 } else if (priv->mode == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
915 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
918 writel(val, priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
922 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
923 return -EINVAL; in rk3568_combphy_cfg()
926 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3568_combphy_cfg()
927 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
928 if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { in rk3568_combphy_cfg()
929 val = readl(priv->mmio + (0xc << 2)); in rk3568_combphy_cfg()
931 writel(val, priv->mmio + (0xc << 2)); in rk3568_combphy_cfg()
933 val = readl(priv->mmio + (0xd << 2)); in rk3568_combphy_cfg()
935 writel(val, priv->mmio + (0xd << 2)); in rk3568_combphy_cfg()
939 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3568_combphy_cfg()
940 val = readl(priv->mmio + (0x7 << 2)); in rk3568_combphy_cfg()
942 writel(val, priv->mmio + (0x7 << 2)); in rk3568_combphy_cfg()
949 /* pipe-phy-grf */
976 /* pipe-grf */
1000 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
1007 for (i = 0; i < priv->num_clks; i++) { in rk3588_combphy_cfg()
1008 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3588_combphy_cfg()
1009 refclk = priv->clks[i].clk; in rk3588_combphy_cfg()
1015 dev_err(priv->dev, "No refclk found\n"); in rk3588_combphy_cfg()
1016 return -EINVAL; in rk3588_combphy_cfg()
1019 switch (priv->mode) { in rk3588_combphy_cfg()
1021 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
1022 val = readl(priv->mmio + (0x1f << 2)); in rk3588_combphy_cfg()
1025 writel(val, priv->mmio + 0x7c); in rk3588_combphy_cfg()
1027 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
1028 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
1029 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
1030 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
1033 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
1034 val = readl(priv->mmio + (0x1f << 2)); in rk3588_combphy_cfg()
1037 writel(val, priv->mmio + 0x7c); in rk3588_combphy_cfg()
1040 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1043 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1046 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1049 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1052 writel(0x4, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
1055 val = readl(priv->mmio + (0x5 << 2)); in rk3588_combphy_cfg()
1058 writel(val, priv->mmio + (0x5 << 2)); in rk3588_combphy_cfg()
1061 writel(0x32, priv->mmio + (0x11 << 2)); in rk3588_combphy_cfg()
1064 writel(0xf0, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
1067 writel(0x0d, priv->mmio + (0x14 << 2)); in rk3588_combphy_cfg()
1069 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
1070 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
1071 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
1075 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1078 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1080 writel(0x8F, priv->mmio + (0x06 << 2)); in rk3588_combphy_cfg()
1082 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
1083 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
1084 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
1085 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
1086 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
1087 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
1092 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
1093 return -EINVAL; in rk3588_combphy_cfg()
1100 param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3588_combphy_cfg()
1101 if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1103 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1106 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1108 val = readl(priv->mmio + (0x0f << 2)); in rk3588_combphy_cfg()
1111 writel(val, priv->mmio + (0x0f << 2)); in rk3588_combphy_cfg()
1112 } else if (priv->mode == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
1114 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1117 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1121 writel(val, priv->mmio + (0x1b << 2)); in rk3588_combphy_cfg()
1125 writel(val, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
1127 writel(val, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
1129 writel(val, priv->mmio + (0xd << 2)); in rk3588_combphy_cfg()
1132 writel(val, priv->mmio + (0xf << 2)); in rk3588_combphy_cfg()
1136 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
1139 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
1140 if (priv->mode == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
1143 writel(val, priv->mmio + 0x74); in rk3588_combphy_cfg()
1146 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1149 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1153 writel(val, priv->mmio + (0x1b << 2)); in rk3588_combphy_cfg()
1157 writel(val, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
1159 writel(val, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
1161 writel(val, priv->mmio + (0xc << 2)); in rk3588_combphy_cfg()
1163 writel(val, priv->mmio + (0xd << 2)); in rk3588_combphy_cfg()
1164 } else if (priv->mode == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1166 val = readl(priv->mmio + (0x1f << 2)); in rk3588_combphy_cfg()
1169 writel(val, priv->mmio + (0x1f << 2)); in rk3588_combphy_cfg()
1171 /* ssc ppm adjust to 3500ppm */ in rk3588_combphy_cfg()
1172 val = readl(priv->mmio + (0x9 << 2)); in rk3588_combphy_cfg()
1175 writel(val, priv->mmio + (0x9 << 2)); in rk3588_combphy_cfg()
1179 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
1180 return -EINVAL; in rk3588_combphy_cfg()
1183 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3588_combphy_cfg()
1184 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
1185 if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { in rk3588_combphy_cfg()
1187 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1190 writel(val, priv->mmio + (0x1b << 2)); in rk3588_combphy_cfg()
1194 writel(val, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
1196 writel(val, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
1198 writel(val, priv->mmio + (0xc << 2)); in rk3588_combphy_cfg()
1200 writel(val, priv->mmio + (0xd << 2)); in rk3588_combphy_cfg()
1204 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3588_combphy_cfg()
1205 val = readl(priv->mmio + (0x7 << 2)); in rk3588_combphy_cfg()
1207 writel(val, priv->mmio + (0x7 << 2)); in rk3588_combphy_cfg()
1209 if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) { in rk3588_combphy_cfg()
1211 writel(0x00, priv->mmio + (0x10 << 2)); in rk3588_combphy_cfg()
1212 writel(0x32, priv->mmio + (0x11 << 2)); in rk3588_combphy_cfg()
1213 writel(0x00, priv->mmio + (0x1b << 2)); in rk3588_combphy_cfg()
1214 writel(0x90, priv->mmio + (0x0a << 2)); in rk3588_combphy_cfg()
1215 writel(0x02, priv->mmio + (0x0b << 2)); in rk3588_combphy_cfg()
1216 writel(0x08, priv->mmio + (0x0c << 2)); in rk3588_combphy_cfg()
1217 writel(0x57, priv->mmio + (0x0d << 2)); in rk3588_combphy_cfg()
1218 writel(0x40, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
1219 writel(0x5f, priv->mmio + (0x0f << 2)); in rk3588_combphy_cfg()
1220 writel(0x10, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
1228 /* pipe-phy-grf */
1250 /* pipe-grf */
1271 .compatible = "rockchip,rk3528-naneng-combphy",
1275 .compatible = "rockchip,rk3562-naneng-combphy",
1279 .compatible = "rockchip,rk3568-naneng-combphy",
1283 .compatible = "rockchip,rk3588-naneng-combphy",
1293 .name = "naneng-combphy",