Lines Matching refs:u3phy_port
230 struct rockchip_u3phy_port *u3phy_port; in rockchip_u3phy_usb2_only_write() local
250 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_usb2_only_write()
252 if (u3phy_port->type == U3PHY_TYPE_PIPE) in rockchip_u3phy_usb2_only_write()
253 writel(0x30, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
272 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_usb2_only_write()
274 if (u3phy_port->type == U3PHY_TYPE_PIPE) in rockchip_u3phy_usb2_only_write()
275 writel(0x20, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
404 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); in rockchip_u3phy_power_on() local
408 dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n", in rockchip_u3phy_power_on()
409 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); in rockchip_u3phy_power_on()
411 if (!u3phy_port->suspended) in rockchip_u3phy_power_on()
418 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rockchip_u3phy_power_on()
429 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true); in rockchip_u3phy_power_on()
446 u3phy_port->suspended = false; in rockchip_u3phy_power_on()
452 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); in rockchip_u3phy_power_off() local
455 dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n", in rockchip_u3phy_power_off()
456 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); in rockchip_u3phy_power_off()
458 if (u3phy_port->suspended) in rockchip_u3phy_power_off()
461 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rockchip_u3phy_power_off()
482 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false); in rockchip_u3phy_power_off()
488 u3phy_port->suspended = true; in rockchip_u3phy_power_off()
497 struct rockchip_u3phy_port *u3phy_port = NULL; in rockchip_u3phy_xlate() local
508 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_xlate()
513 if (!u3phy_port) { in rockchip_u3phy_xlate()
518 return u3phy_port->phy; in rockchip_u3phy_xlate()
541 struct rockchip_u3phy_port *u3phy_port = in rockchip_u3phy_um_sm_work() local
544 dev_get_drvdata(u3phy_port->phy->dev.parent); in rockchip_u3phy_um_sm_work()
551 mutex_lock(&u3phy_port->mutex); in rockchip_u3phy_um_sm_work()
574 dev_dbg(&u3phy_port->phy->dev, "HS online\n"); in rockchip_u3phy_um_sm_work()
586 if (!u3phy_port->suspended) { in rockchip_u3phy_um_sm_work()
588 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); in rockchip_u3phy_um_sm_work()
593 if (u3phy_port->suspended) { in rockchip_u3phy_um_sm_work()
594 dev_dbg(&u3phy_port->phy->dev, "Connected\n"); in rockchip_u3phy_um_sm_work()
595 rockchip_u3phy_power_on(u3phy_port->phy); in rockchip_u3phy_um_sm_work()
596 u3phy_port->suspended = false; in rockchip_u3phy_um_sm_work()
599 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); in rockchip_u3phy_um_sm_work()
603 if (!u3phy_port->suspended) { in rockchip_u3phy_um_sm_work()
604 dev_dbg(&u3phy_port->phy->dev, "Disconnected\n"); in rockchip_u3phy_um_sm_work()
605 rockchip_u3phy_power_off(u3phy_port->phy); in rockchip_u3phy_um_sm_work()
606 u3phy_port->suspended = true; in rockchip_u3phy_um_sm_work()
622 mutex_unlock(&u3phy_port->mutex); in rockchip_u3phy_um_sm_work()
625 dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n"); in rockchip_u3phy_um_sm_work()
630 mutex_unlock(&u3phy_port->mutex); in rockchip_u3phy_um_sm_work()
631 schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY); in rockchip_u3phy_um_sm_work()
636 struct rockchip_u3phy_port *u3phy_port = data; in rockchip_u3phy_um_ls_irq() local
638 dev_get_drvdata(u3phy_port->phy->dev.parent); in rockchip_u3phy_um_ls_irq()
646 mutex_lock(&u3phy_port->mutex); in rockchip_u3phy_um_ls_irq()
652 mutex_unlock(&u3phy_port->mutex); in rockchip_u3phy_um_ls_irq()
659 if (u3phy_port->suspended) { in rockchip_u3phy_um_ls_irq()
661 rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work); in rockchip_u3phy_um_ls_irq()
721 struct rockchip_u3phy_port *u3phy_port, in rockchip_u3phy_port_init() argument
730 mutex_init(&u3phy_port->mutex); in rockchip_u3phy_port_init()
731 u3phy_port->suspended = true; /* initial status */ in rockchip_u3phy_port_init()
739 u3phy_port->phy = phy; in rockchip_u3phy_port_init()
748 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); in rockchip_u3phy_port_init()
749 if (IS_ERR(u3phy_port->base)) { in rockchip_u3phy_port_init()
751 return PTR_ERR(u3phy_port->base); in rockchip_u3phy_port_init()
755 u3phy_port->type = U3PHY_TYPE_PIPE; in rockchip_u3phy_port_init()
756 u3phy_port->refclk_25m_quirk = in rockchip_u3phy_port_init()
760 u3phy_port->type = U3PHY_TYPE_UTMI; in rockchip_u3phy_port_init()
761 INIT_DELAYED_WORK(&u3phy_port->um_sm_work, in rockchip_u3phy_port_init()
767 u3phy_port); in rockchip_u3phy_port_init()
776 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); in rockchip_u3phy_port_init()
781 phy_set_drvdata(u3phy_port->phy, u3phy_port); in rockchip_u3phy_port_init()
901 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_probe() local
903 u3phy_port->index = index; in rockchip_u3phy_probe()
904 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np); in rockchip_u3phy_probe()
942 struct rockchip_u3phy_port *u3phy_port, in rk3328_u3phy_pipe_power() argument
948 reg = readl(u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
950 writel(reg, u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
952 reg = readl(u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
954 writel(reg, u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
956 reg = readl(u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
958 writel(reg, u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
960 reg = readl(u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
962 writel(reg, u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
964 reg = readl(u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
967 writel(reg, u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
971 reg = readl(u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
973 writel(reg, u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
975 reg = readl(u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
977 writel(reg, u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
979 reg = readl(u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
981 writel(reg, u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
983 reg = readl(u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
985 writel(reg, u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
987 reg = readl(u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
990 writel(reg, u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
997 struct rockchip_u3phy_port *u3phy_port, in rk3328_u3phy_tuning() argument
1000 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rk3328_u3phy_tuning()
1022 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
1023 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); in rk3328_u3phy_tuning()
1024 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1025 } else if (u3phy_port->type == U3PHY_TYPE_PIPE) { in rk3328_u3phy_tuning()
1026 if (u3phy_port->refclk_25m_quirk) { in rk3328_u3phy_tuning()
1029 writel(0x64, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1030 writel(0x64, u3phy_port->base + 0x028); in rk3328_u3phy_tuning()
1031 writel(0x01, u3phy_port->base + 0x020); in rk3328_u3phy_tuning()
1032 writel(0x21, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
1033 writel(0x06, u3phy_port->base + 0x108); in rk3328_u3phy_tuning()
1034 writel(0x00, u3phy_port->base + 0x118); in rk3328_u3phy_tuning()
1037 writel(0x80, u3phy_port->base + 0x10c); in rk3328_u3phy_tuning()
1038 writel(0x01, u3phy_port->base + 0x118); in rk3328_u3phy_tuning()
1039 writel(0x38, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1040 writel(0x83, u3phy_port->base + 0x020); in rk3328_u3phy_tuning()
1041 writel(0x02, u3phy_port->base + 0x108); in rk3328_u3phy_tuning()
1046 writel(0x08, u3phy_port->base + 0x000); in rk3328_u3phy_tuning()
1047 writel(0x0c, u3phy_port->base + 0x120); in rk3328_u3phy_tuning()
1050 writel(0x70, u3phy_port->base + 0x150); in rk3328_u3phy_tuning()
1051 writel(0x12, u3phy_port->base + 0x0c8); in rk3328_u3phy_tuning()
1052 writel(0x05, u3phy_port->base + 0x148); in rk3328_u3phy_tuning()
1053 writel(0x08, u3phy_port->base + 0x068); in rk3328_u3phy_tuning()
1054 writel(0xf0, u3phy_port->base + 0x1c4); in rk3328_u3phy_tuning()
1055 writel(0xff, u3phy_port->base + 0x070); in rk3328_u3phy_tuning()
1056 writel(0x0f, u3phy_port->base + 0x06c); in rk3328_u3phy_tuning()
1057 writel(0xe0, u3phy_port->base + 0x060); in rk3328_u3phy_tuning()
1064 writel(0x08, u3phy_port->base + 0x180); in rk3328_u3phy_tuning()