Lines Matching refs:u3phy
183 static int rockchip_set_vbus_power(struct rockchip_u3phy *u3phy, bool en) in rockchip_set_vbus_power() argument
187 if (!u3phy->vbus) in rockchip_set_vbus_power()
190 if (en && !u3phy->vbus_enabled) { in rockchip_set_vbus_power()
191 ret = regulator_enable(u3phy->vbus); in rockchip_set_vbus_power()
193 dev_err(u3phy->dev, in rockchip_set_vbus_power()
195 } else if (!en && u3phy->vbus_enabled) { in rockchip_set_vbus_power()
196 ret = regulator_disable(u3phy->vbus); in rockchip_set_vbus_power()
200 u3phy->vbus_enabled = en; in rockchip_set_vbus_power()
207 struct rockchip_u3phy *u3phy = s->private; in rockchip_u3phy_usb2_only_show() local
209 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) in rockchip_u3phy_usb2_only_show()
210 dev_info(u3phy->dev, "u2\n"); in rockchip_u3phy_usb2_only_show()
212 dev_info(u3phy->dev, "u3\n"); in rockchip_u3phy_usb2_only_show()
229 struct rockchip_u3phy *u3phy = s->private; in rockchip_u3phy_usb2_only_write() local
238 param_exped(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
239 &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) { in rockchip_u3phy_usb2_only_write()
240 dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n"); in rockchip_u3phy_usb2_only_write()
242 rockchip_set_vbus_power(u3phy, false); in rockchip_u3phy_usb2_only_write()
244 param_write(u3phy->grf, in rockchip_u3phy_usb2_only_write()
245 &u3phy->cfgs->grfcfg.u3_disable, false); in rockchip_u3phy_usb2_only_write()
246 param_write(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
247 &u3phy->cfgs->grfcfg.u2_only_ctrl, false); in rockchip_u3phy_usb2_only_write()
250 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_usb2_only_write()
256 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); in rockchip_u3phy_usb2_only_write()
258 rockchip_set_vbus_power(u3phy, true); in rockchip_u3phy_usb2_only_write()
260 param_exped(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
261 &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) { in rockchip_u3phy_usb2_only_write()
262 dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n"); in rockchip_u3phy_usb2_only_write()
264 rockchip_set_vbus_power(u3phy, false); in rockchip_u3phy_usb2_only_write()
266 param_write(u3phy->grf, in rockchip_u3phy_usb2_only_write()
267 &u3phy->cfgs->grfcfg.u3_disable, true); in rockchip_u3phy_usb2_only_write()
268 param_write(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
269 &u3phy->cfgs->grfcfg.u2_only_ctrl, true); in rockchip_u3phy_usb2_only_write()
272 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_usb2_only_write()
278 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); in rockchip_u3phy_usb2_only_write()
280 rockchip_set_vbus_power(u3phy, true); in rockchip_u3phy_usb2_only_write()
282 dev_info(u3phy->dev, "Same or illegal mode\n"); in rockchip_u3phy_usb2_only_write()
296 static void rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy) in rockchip_u3phy_debugfs_init() argument
300 root = debugfs_create_dir(dev_name(u3phy->dev), NULL); in rockchip_u3phy_debugfs_init()
302 u3phy, &rockchip_u3phy_usb2_only_fops); in rockchip_u3phy_debugfs_init()
325 static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy, in rockchip_u3phy_rest_deassert() argument
331 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); in rockchip_u3phy_rest_deassert()
333 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_deassert()
334 reset_control_deassert(u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
340 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); in rockchip_u3phy_rest_deassert()
342 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_deassert()
343 reset_control_deassert(u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
349 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); in rockchip_u3phy_rest_deassert()
351 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_deassert()
352 reset_control_deassert(u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
356 static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy) in rockchip_u3phy_rest_assert() argument
360 dev_dbg(u3phy->dev, "assert u3phy reset\n"); in rockchip_u3phy_rest_assert()
362 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_assert()
363 reset_control_assert(u3phy->rsts[rst]); in rockchip_u3phy_rest_assert()
366 static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy) in rockchip_u3phy_clk_enable() argument
370 for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) { in rockchip_u3phy_clk_enable()
371 ret = clk_prepare_enable(u3phy->clks[clk]); in rockchip_u3phy_clk_enable()
379 clk_disable_unprepare(u3phy->clks[clk]); in rockchip_u3phy_clk_enable()
383 static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy) in rockchip_u3phy_clk_disable() argument
388 if (u3phy->clks[clk]) in rockchip_u3phy_clk_disable()
389 clk_disable_unprepare(u3phy->clks[clk]); in rockchip_u3phy_clk_disable()
405 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); in rockchip_u3phy_power_on() local
414 ret = rockchip_u3phy_clk_enable(u3phy); in rockchip_u3phy_power_on()
419 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
420 &u3phy->cfgs->grfcfg.um_suspend, false); in rockchip_u3phy_power_on()
423 if (param_exped(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
424 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2)) in rockchip_u3phy_power_on()
427 if (u3phy->cfgs->phy_pipe_power) { in rockchip_u3phy_power_on()
428 dev_dbg(u3phy->dev, "do pipe power up\n"); in rockchip_u3phy_power_on()
429 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true); in rockchip_u3phy_power_on()
433 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
434 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); in rockchip_u3phy_power_on()
438 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
439 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2], in rockchip_u3phy_power_on()
445 rockchip_set_vbus_power(u3phy, true); in rockchip_u3phy_power_on()
453 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); in rockchip_u3phy_power_off() local
462 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
463 &u3phy->cfgs->grfcfg.um_suspend, true); in rockchip_u3phy_power_off()
466 if (param_exped(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
467 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3)) in rockchip_u3phy_power_off()
471 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
472 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); in rockchip_u3phy_power_off()
476 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
477 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true); in rockchip_u3phy_power_off()
480 if (u3phy->cfgs->phy_pipe_power) { in rockchip_u3phy_power_off()
481 dev_dbg(u3phy->dev, "do pipe power down\n"); in rockchip_u3phy_power_off()
482 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false); in rockchip_u3phy_power_off()
487 rockchip_u3phy_clk_disable(u3phy); in rockchip_u3phy_power_off()
496 struct rockchip_u3phy *u3phy = dev_get_drvdata(dev); in rockchip_u3phy_xlate() local
507 if (phy_np == u3phy->ports[index].phy->dev.of_node) { in rockchip_u3phy_xlate()
508 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_xlate()
543 struct rockchip_u3phy *u3phy = in rockchip_u3phy_um_sm_work() local
545 unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend - in rockchip_u3phy_um_sm_work()
546 u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1; in rockchip_u3phy_um_sm_work()
553 ret = regmap_read(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
554 u3phy->cfgs->grfcfg.um_ls.offset, &ul); in rockchip_u3phy_um_sm_work()
558 ret = regmap_read(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
559 u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd); in rockchip_u3phy_um_sm_work()
563 uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend, in rockchip_u3phy_um_sm_work()
564 u3phy->cfgs->grfcfg.um_hstdct.bitstart); in rockchip_u3phy_um_sm_work()
565 ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend, in rockchip_u3phy_um_sm_work()
566 u3phy->cfgs->grfcfg.um_ls.bitstart); in rockchip_u3phy_um_sm_work()
569 state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) | in rockchip_u3phy_um_sm_work()
570 (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh); in rockchip_u3phy_um_sm_work()
613 param_write(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
614 &u3phy->cfgs->grfcfg.ls_det_st, true); in rockchip_u3phy_um_sm_work()
615 param_write(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
616 &u3phy->cfgs->grfcfg.ls_det_en, true); in rockchip_u3phy_um_sm_work()
637 struct rockchip_u3phy *u3phy = in rockchip_u3phy_um_ls_irq() local
640 if (!param_exped(u3phy->u3phy_grf, in rockchip_u3phy_um_ls_irq()
641 &u3phy->cfgs->grfcfg.ls_det_st, in rockchip_u3phy_um_ls_irq()
642 u3phy->cfgs->grfcfg.ls_det_st.dvalue)) in rockchip_u3phy_um_ls_irq()
645 dev_dbg(u3phy->dev, "utmi linestate interrupt\n"); in rockchip_u3phy_um_ls_irq()
649 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false); in rockchip_u3phy_um_ls_irq()
650 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true); in rockchip_u3phy_um_ls_irq()
660 dev_dbg(u3phy->dev, "schedule utmi sm work\n"); in rockchip_u3phy_um_ls_irq()
667 static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy, in rockchip_u3phy_parse_dt() argument
675 u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate"); in rockchip_u3phy_parse_dt()
676 if (u3phy->um_ls_irq < 0) { in rockchip_u3phy_parse_dt()
682 u3phy->vbus = devm_regulator_get_optional(dev, "vbus"); in rockchip_u3phy_parse_dt()
683 if (IS_ERR(u3phy->vbus)) { in rockchip_u3phy_parse_dt()
684 ret = PTR_ERR(u3phy->vbus); in rockchip_u3phy_parse_dt()
689 u3phy->vbus = NULL; in rockchip_u3phy_parse_dt()
693 u3phy->clks[clk] = of_clk_get(np, clk); in rockchip_u3phy_parse_dt()
694 if (IS_ERR(u3phy->clks[clk])) { in rockchip_u3phy_parse_dt()
695 ret = PTR_ERR(u3phy->clks[clk]); in rockchip_u3phy_parse_dt()
698 u3phy->clks[clk] = NULL; in rockchip_u3phy_parse_dt()
704 u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i)); in rockchip_u3phy_parse_dt()
705 if (IS_ERR(u3phy->rsts[i])) { in rockchip_u3phy_parse_dt()
708 u3phy->rsts[i] = NULL; in rockchip_u3phy_parse_dt()
716 clk_put(u3phy->clks[clk]); in rockchip_u3phy_parse_dt()
720 static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy, in rockchip_u3phy_port_init() argument
728 dev_dbg(u3phy->dev, "u3phy port initialize\n"); in rockchip_u3phy_port_init()
733 phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops); in rockchip_u3phy_port_init()
735 dev_err(u3phy->dev, "failed to create phy\n"); in rockchip_u3phy_port_init()
743 dev_err(u3phy->dev, "failed to get address resource(np-%s)\n", in rockchip_u3phy_port_init()
750 dev_err(u3phy->dev, "failed to remap phy regs\n"); in rockchip_u3phy_port_init()
764 ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq, in rockchip_u3phy_port_init()
769 dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n"); in rockchip_u3phy_port_init()
774 if (u3phy->cfgs->phy_tuning) { in rockchip_u3phy_port_init()
775 dev_dbg(u3phy->dev, "do u3phy tuning\n"); in rockchip_u3phy_port_init()
776 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); in rockchip_u3phy_port_init()
787 struct rockchip_u3phy *u3phy = in rockchip_u3phy_on_init() local
790 rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST); in rockchip_u3phy_on_init()
796 struct rockchip_u3phy *u3phy = in rockchip_u3phy_on_shutdown() local
801 if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN && in rockchip_u3phy_on_shutdown()
803 reset_control_assert(u3phy->rsts[rst]); in rockchip_u3phy_on_shutdown()
810 struct rockchip_u3phy *u3phy = in rockchip_u3phy_on_disconnect() local
813 dev_info(u3phy->dev, "%s device has disconnected\n", in rockchip_u3phy_on_disconnect()
828 struct rockchip_u3phy *u3phy; in rockchip_u3phy_probe() local
840 u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL); in rockchip_u3phy_probe()
841 if (!u3phy) in rockchip_u3phy_probe()
844 u3phy->u3phy_grf = in rockchip_u3phy_probe()
846 if (IS_ERR(u3phy->u3phy_grf)) in rockchip_u3phy_probe()
847 return PTR_ERR(u3phy->u3phy_grf); in rockchip_u3phy_probe()
849 u3phy->grf = in rockchip_u3phy_probe()
851 if (IS_ERR(u3phy->grf)) { in rockchip_u3phy_probe()
853 return PTR_ERR(u3phy->grf); in rockchip_u3phy_probe()
862 u3phy->dev = dev; in rockchip_u3phy_probe()
863 u3phy->vbus_enabled = false; in rockchip_u3phy_probe()
865 platform_set_drvdata(pdev, u3phy); in rockchip_u3phy_probe()
871 u3phy->cfgs = &phy_cfgs[index]; in rockchip_u3phy_probe()
878 if (!u3phy->cfgs) { in rockchip_u3phy_probe()
884 ret = rockchip_u3phy_parse_dt(u3phy, pdev); in rockchip_u3phy_probe()
890 ret = rockchip_u3phy_clk_enable(u3phy); in rockchip_u3phy_probe()
896 rockchip_u3phy_rest_assert(u3phy); in rockchip_u3phy_probe()
897 rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST); in rockchip_u3phy_probe()
901 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_probe()
904 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np); in rockchip_u3phy_probe()
921 rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST); in rockchip_u3phy_probe()
922 rockchip_u3phy_clk_disable(u3phy); in rockchip_u3phy_probe()
924 u3phy->usb_phy.dev = dev; in rockchip_u3phy_probe()
925 u3phy->usb_phy.init = rockchip_u3phy_on_init; in rockchip_u3phy_probe()
926 u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown; in rockchip_u3phy_probe()
927 u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect; in rockchip_u3phy_probe()
928 usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3); in rockchip_u3phy_probe()
929 ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier); in rockchip_u3phy_probe()
931 rockchip_u3phy_debugfs_init(u3phy); in rockchip_u3phy_probe()
941 static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy, in rk3328_u3phy_pipe_power() argument
996 static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy, in rk3328_u3phy_tuning() argument
1011 u3phy->apbcfg.u2_pre_emp = 0x0f; in rk3328_u3phy_tuning()
1014 u3phy->apbcfg.u2_pre_emp_sth = 0x41; in rk3328_u3phy_tuning()
1017 u3phy->apbcfg.u2_odt_tuning = 0xb5; in rk3328_u3phy_tuning()
1020 &u3phy->apbcfg.u2_odt_tuning); in rk3328_u3phy_tuning()
1022 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
1023 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); in rk3328_u3phy_tuning()
1024 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1027 dev_dbg(u3phy->dev, "switch to 25m refclk\n"); in rk3328_u3phy_tuning()
1066 dev_err(u3phy->dev, "invalid u3phy port type\n"); in rk3328_u3phy_tuning()