147 	const struct rockchip_u3phy_cfg *cfgs;  member
209 	if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1))  in rockchip_u3phy_usb2_only_show()
239 			&u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {  in rockchip_u3phy_usb2_only_write()
245 			    &u3phy->cfgs->grfcfg.u3_disable, false);  in rockchip_u3phy_usb2_only_write()
247 			    &u3phy->cfgs->grfcfg.u2_only_ctrl, false);  in rockchip_u3phy_usb2_only_write()
261 			       &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) {  in rockchip_u3phy_usb2_only_write()
267 			    &u3phy->cfgs->grfcfg.u3_disable, true);  in rockchip_u3phy_usb2_only_write()
269 			    &u3phy->cfgs->grfcfg.u2_only_ctrl, true);  in rockchip_u3phy_usb2_only_write()
420 			    &u3phy->cfgs->grfcfg.um_suspend, false);  in rockchip_u3phy_power_on()
424 				&u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2))  in rockchip_u3phy_power_on()
427 		if (u3phy->cfgs->phy_pipe_power) {  in rockchip_u3phy_power_on()
429 			u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true);  in rockchip_u3phy_power_on()
434 			    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);  in rockchip_u3phy_power_on()
439 			    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2],  in rockchip_u3phy_power_on()
463 			    &u3phy->cfgs->grfcfg.um_suspend, true);  in rockchip_u3phy_power_off()
467 				&u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3))  in rockchip_u3phy_power_off()
472 			    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);  in rockchip_u3phy_power_off()
477 			    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true);  in rockchip_u3phy_power_off()
480 		if (u3phy->cfgs->phy_pipe_power) {  in rockchip_u3phy_power_off()
482 			u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false);  in rockchip_u3phy_power_off()
545 	unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend -  in rockchip_u3phy_um_sm_work()
546 			u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1;  in rockchip_u3phy_um_sm_work()
554 			  u3phy->cfgs->grfcfg.um_ls.offset, &ul);  in rockchip_u3phy_um_sm_work()
559 			  u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd);  in rockchip_u3phy_um_sm_work()
563 	uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend,  in rockchip_u3phy_um_sm_work()
564 			   u3phy->cfgs->grfcfg.um_hstdct.bitstart);  in rockchip_u3phy_um_sm_work()
565 	ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend,  in rockchip_u3phy_um_sm_work()
566 			  u3phy->cfgs->grfcfg.um_ls.bitstart);  in rockchip_u3phy_um_sm_work()
569 	state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) |  in rockchip_u3phy_um_sm_work()
570 		(((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh);  in rockchip_u3phy_um_sm_work()
614 			    &u3phy->cfgs->grfcfg.ls_det_st, true);  in rockchip_u3phy_um_sm_work()
616 			    &u3phy->cfgs->grfcfg.ls_det_en, true);  in rockchip_u3phy_um_sm_work()
641 			 &u3phy->cfgs->grfcfg.ls_det_st,  in rockchip_u3phy_um_ls_irq()
642 			 u3phy->cfgs->grfcfg.ls_det_st.dvalue))  in rockchip_u3phy_um_ls_irq()
649 	param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false);  in rockchip_u3phy_um_ls_irq()
650 	param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);  in rockchip_u3phy_um_ls_irq()
774 	if (u3phy->cfgs->phy_tuning) {  in rockchip_u3phy_port_init()
776 		ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);  in rockchip_u3phy_port_init()
871 			u3phy->cfgs = &phy_cfgs[index];  in rockchip_u3phy_probe()
878 	if (!u3phy->cfgs) {  in rockchip_u3phy_probe()