Lines Matching refs:inno
215 void (*init)(struct inno_hdmi_phy *inno);
216 int (*power_on)(struct inno_hdmi_phy *inno,
219 void (*power_off)(struct inno_hdmi_phy *inno);
220 int (*pre_pll_update)(struct inno_hdmi_phy *inno,
222 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno,
376 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) in inno_write() argument
378 regmap_write(inno->regmap, reg * 4, val); in inno_write()
381 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) in inno_read() argument
385 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
390 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() argument
393 regmap_update_bits(inno->regmap, reg * 4, mask, val); in inno_update_bits()
396 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate) in inno_hdmi_phy_get_tmdsclk() argument
398 int bus_width = phy_get_bus_width(inno->phy); in inno_hdmi_phy_get_tmdsclk()
429 struct inno_hdmi_phy *inno = dev_id; in inno_hdmi_phy_hardirq() local
432 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_hardirq()
435 intr_stat1 = inno_read(inno, 0x04); in inno_hdmi_phy_hardirq()
436 intr_stat2 = inno_read(inno, 0x06); in inno_hdmi_phy_hardirq()
437 intr_stat3 = inno_read(inno, 0x08); in inno_hdmi_phy_hardirq()
440 inno_write(inno, 0x04, intr_stat1); in inno_hdmi_phy_hardirq()
442 inno_write(inno, 0x06, intr_stat2); in inno_hdmi_phy_hardirq()
444 inno_write(inno, 0x08, intr_stat3); in inno_hdmi_phy_hardirq()
454 struct inno_hdmi_phy *inno = dev_id; in inno_hdmi_phy_irq() local
456 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_irq()
459 inno_update_bits(inno, 0x02, 1, 0); in inno_hdmi_phy_irq()
464 inno_update_bits(inno, 0x02, 1, 1); in inno_hdmi_phy_irq()
474 struct inno_hdmi_phy *inno = phy_get_drvdata(phy); in inno_hdmi_phy_power_on() local
476 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
477 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); in inno_hdmi_phy_power_on()
480 if (inno->phy_cfg) in inno_hdmi_phy_power_on()
481 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
484 dev_err(inno->dev, "TMDS clock is zero!\n"); in inno_hdmi_phy_power_on()
488 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && in inno_hdmi_phy_power_on()
491 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && in inno_hdmi_phy_power_on()
492 tmdsclock <= 33750000 && inno->efuse_flag) in inno_hdmi_phy_power_on()
494 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) in inno_hdmi_phy_power_on()
509 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
510 inno_hdmi_phy_clk_set_rate(&inno->hw, inno->pixclock, 0); in inno_hdmi_phy_power_on()
512 if (inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
513 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
520 struct inno_hdmi_phy *inno = phy_get_drvdata(phy); in inno_hdmi_phy_power_off() local
522 if (inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
523 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
525 inno->tmdsclock = 0; in inno_hdmi_phy_power_off()
526 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); in inno_hdmi_phy_power_off()
539 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_clk_is_prepared() local
542 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_is_prepared()
543 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK; in inno_hdmi_phy_clk_is_prepared()
545 status = inno_read(inno, 0xa0) & 1; in inno_hdmi_phy_clk_is_prepared()
552 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_clk_prepare() local
554 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_prepare()
555 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, in inno_hdmi_phy_clk_prepare()
558 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_clk_prepare()
565 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_clk_unprepare() local
567 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_unprepare()
568 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, in inno_hdmi_phy_clk_unprepare()
571 inno_update_bits(inno, 0xa0, 1, 1); in inno_hdmi_phy_clk_unprepare()
577 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_clk_recalc_rate() local
579 if (inno->plat_data->ops->recalc_rate) in inno_hdmi_phy_clk_recalc_rate()
580 return inno->plat_data->ops->recalc_rate(inno, parent_rate); in inno_hdmi_phy_clk_recalc_rate()
582 return inno->pixclock; in inno_hdmi_phy_clk_recalc_rate()
590 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_clk_round_rate() local
591 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_clk_round_rate()
606 if (!inno->phy_cfg) in inno_hdmi_phy_clk_round_rate()
610 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { in inno_hdmi_phy_clk_round_rate()
611 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) in inno_hdmi_phy_clk_round_rate()
615 if (inno->phy_cfg[i].tmdsclock == ~0UL) in inno_hdmi_phy_clk_round_rate()
624 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_clk_set_rate() local
626 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_clk_set_rate()
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n", in inno_hdmi_phy_clk_set_rate()
631 if (inno->tmdsclock == tmdsclock) in inno_hdmi_phy_clk_set_rate()
639 dev_err(inno->dev, "unsupported rate %lu\n", rate); in inno_hdmi_phy_clk_set_rate()
643 if (inno->plat_data->ops->pre_pll_update) in inno_hdmi_phy_clk_set_rate()
644 inno->plat_data->ops->pre_pll_update(inno, cfg); in inno_hdmi_phy_clk_set_rate()
646 inno->pixclock = rate; in inno_hdmi_phy_clk_set_rate()
647 inno->tmdsclock = tmdsclock; in inno_hdmi_phy_clk_set_rate()
661 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno) in inno_hdmi_phy_clk_register() argument
663 struct device *dev = inno->dev; in inno_hdmi_phy_clk_register()
671 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) in inno_hdmi_phy_clk_register()
694 inno->hw.init = &init; in inno_hdmi_phy_clk_register()
696 inno->pclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
697 if (IS_ERR(inno->pclk)) { in inno_hdmi_phy_clk_register()
698 ret = PTR_ERR(inno->pclk); in inno_hdmi_phy_clk_register()
703 ret = of_clk_add_provider(clk_np, of_clk_src_simple_get, inno->pclk); in inno_hdmi_phy_clk_register()
713 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3228_power_on() argument
721 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); in inno_hdmi_phy_rk3228_power_on()
724 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
725 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
730 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
734 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
735 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
741 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
746 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
750 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
754 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
757 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP); in inno_hdmi_phy_rk3228_power_on()
758 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); in inno_hdmi_phy_rk3228_power_on()
761 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE); in inno_hdmi_phy_rk3228_power_on()
764 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE); in inno_hdmi_phy_rk3228_power_on()
768 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) { in inno_hdmi_phy_rk3228_power_on()
770 dev_err(inno->dev, "Post-PLL unlock\n"); in inno_hdmi_phy_rk3228_power_on()
782 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE); in inno_hdmi_phy_rk3228_power_on()
786 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3228_power_off() argument
789 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE); in inno_hdmi_phy_rk3228_power_off()
792 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE); in inno_hdmi_phy_rk3228_power_off()
795 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_off()
798 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3228_init() argument
812 inno_update_bits(inno, 0x01, m, v); in inno_hdmi_phy_rk3228_init()
813 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN); in inno_hdmi_phy_rk3228_init()
819 if ((inno_read(inno, 0xe9) != 0xe4 || inno_read(inno, 0xea) != 0x50)) { in inno_hdmi_phy_rk3228_init()
820 dev_info(inno->dev, "phy had been powered up\n"); in inno_hdmi_phy_rk3228_init()
821 inno->phy->power_count = 1; in inno_hdmi_phy_rk3228_init()
823 inno_hdmi_phy_rk3228_power_off(inno); in inno_hdmi_phy_rk3228_init()
825 inno_update_bits(inno, 0xaa, in inno_hdmi_phy_rk3228_init()
829 cell = nvmem_cell_get(inno->dev, "hdmi_phy_flag"); in inno_hdmi_phy_rk3228_init()
831 dev_err(inno->dev, in inno_hdmi_phy_rk3228_init()
838 inno->efuse_flag = efuse_buf[0] ? true : false; in inno_hdmi_phy_rk3228_init()
843 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3228_pre_pll_update() argument
850 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_pre_pll_update()
855 inno_update_bits(inno, 0xe2, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
857 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
862 inno_update_bits(inno, 0xe4, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
867 inno_update_bits(inno, 0xe5, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
874 inno_update_bits(inno, 0xe6, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
877 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); in inno_hdmi_phy_rk3228_pre_pll_update()
881 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) { in inno_hdmi_phy_rk3228_pre_pll_update()
883 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3228_pre_pll_update()
895 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3328_power_on() argument
903 inno_update_bits(inno, 0x02, 1, 0); in inno_hdmi_phy_rk3328_power_on()
905 inno_update_bits(inno, 0xaa, 1, 1); in inno_hdmi_phy_rk3328_power_on()
908 inno_write(inno, 0xac, val); in inno_hdmi_phy_rk3328_power_on()
910 inno_write(inno, 0xaa, 2); in inno_hdmi_phy_rk3328_power_on()
912 inno_write(inno, 0xab, val); in inno_hdmi_phy_rk3328_power_on()
915 inno_write(inno, 0xad, val); in inno_hdmi_phy_rk3328_power_on()
917 inno_write(inno, 0xab, val); in inno_hdmi_phy_rk3328_power_on()
918 inno_write(inno, 0xaa, 0x0e); in inno_hdmi_phy_rk3328_power_on()
922 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); in inno_hdmi_phy_rk3328_power_on()
931 inno_write(inno, 0xc8, 0); in inno_hdmi_phy_rk3328_power_on()
932 inno_write(inno, 0xc9, 0); in inno_hdmi_phy_rk3328_power_on()
933 inno_write(inno, 0xca, 0); in inno_hdmi_phy_rk3328_power_on()
934 inno_write(inno, 0xcb, 0); in inno_hdmi_phy_rk3328_power_on()
938 val = clk_get_rate(inno->sysclk) / 100000; in inno_hdmi_phy_rk3328_power_on()
939 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80); in inno_hdmi_phy_rk3328_power_on()
940 inno_write(inno, 0xc6, val & 0xff); in inno_hdmi_phy_rk3328_power_on()
941 inno_write(inno, 0xc7, 3 << 1); in inno_hdmi_phy_rk3328_power_on()
942 inno_write(inno, 0xc5, ((val >> 8) & 0xff)); in inno_hdmi_phy_rk3328_power_on()
944 inno_write(inno, 0xc5, 0x81); in inno_hdmi_phy_rk3328_power_on()
947 inno_write(inno, 0xc8, 0x30); in inno_hdmi_phy_rk3328_power_on()
949 inno_write(inno, 0xc9, 0x10); in inno_hdmi_phy_rk3328_power_on()
950 inno_write(inno, 0xca, 0x10); in inno_hdmi_phy_rk3328_power_on()
951 inno_write(inno, 0xcb, 0x10); in inno_hdmi_phy_rk3328_power_on()
956 do_div(temp, inno->tmdsclock); in inno_hdmi_phy_rk3328_power_on()
957 inno_write(inno, 0xd8, (temp >> 8) & 0xff); in inno_hdmi_phy_rk3328_power_on()
958 inno_write(inno, 0xd9, temp & 0xff); in inno_hdmi_phy_rk3328_power_on()
961 inno_update_bits(inno, 0xaa, 1, 0); in inno_hdmi_phy_rk3328_power_on()
963 inno_update_bits(inno, 0xb0, 4, 4); in inno_hdmi_phy_rk3328_power_on()
964 inno_write(inno, 0xb2, 0x0f); in inno_hdmi_phy_rk3328_power_on()
968 if (inno_read(inno, 0xaf) & 1) in inno_hdmi_phy_rk3328_power_on()
972 if (!(inno_read(inno, 0xaf) & 1)) { in inno_hdmi_phy_rk3328_power_on()
973 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3328_power_on()
979 inno_update_bits(inno, 0x02, 1, 1); in inno_hdmi_phy_rk3328_power_on()
982 inno_write(inno, 0x05, 0x22); in inno_hdmi_phy_rk3328_power_on()
983 inno_write(inno, 0x07, 0x22); in inno_hdmi_phy_rk3328_power_on()
987 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3328_power_off() argument
990 inno_write(inno, 0xb2, 0); in inno_hdmi_phy_rk3328_power_off()
992 inno_update_bits(inno, 0xb0, 4, 0); in inno_hdmi_phy_rk3328_power_off()
994 inno_update_bits(inno, 0xaa, 1, 1); in inno_hdmi_phy_rk3328_power_off()
997 inno_write(inno, 0x05, 0); in inno_hdmi_phy_rk3328_power_off()
998 inno_write(inno, 0x07, 0); in inno_hdmi_phy_rk3328_power_off()
1001 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3328_init() argument
1007 inno_write(inno, 0x01, 0x07); in inno_hdmi_phy_rk3328_init()
1008 inno_write(inno, 0x02, 0x91); in inno_hdmi_phy_rk3328_init()
1014 if ((inno_read(inno, 0xc8) & 0xc0) == 0) { in inno_hdmi_phy_rk3328_init()
1015 dev_info(inno->dev, "phy had been powered up\n"); in inno_hdmi_phy_rk3328_init()
1016 inno->phy->power_count = 1; in inno_hdmi_phy_rk3328_init()
1019 inno_hdmi_phy_rk3328_power_off(inno); in inno_hdmi_phy_rk3328_init()
1024 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3328_pre_pll_update() argument
1030 inno_update_bits(inno, 0xa0, 1, 1); in inno_hdmi_phy_rk3328_pre_pll_update()
1032 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3328_pre_pll_update()
1033 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3328_pre_pll_update()
1038 inno_write(inno, 0xa2, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1039 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3328_pre_pll_update()
1042 inno_write(inno, 0xa5, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1045 inno_write(inno, 0xa6, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1049 inno_write(inno, 0xa4, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1053 inno_write(inno, 0xd3, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1055 inno_write(inno, 0xd2, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1057 inno_write(inno, 0xd1, val); in inno_hdmi_phy_rk3328_pre_pll_update()
1059 inno_write(inno, 0xd3, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
1060 inno_write(inno, 0xd2, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
1061 inno_write(inno, 0xd1, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
1065 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
1069 if (inno_read(inno, 0xa9) & 1) in inno_hdmi_phy_rk3328_pre_pll_update()
1074 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3328_pre_pll_update()
1082 inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, in inno_hdmi_rk3328_phy_pll_recalc_rate() argument
1090 nd = inno_read(inno, 0xa1) & 0x3f; in inno_hdmi_rk3328_phy_pll_recalc_rate()
1091 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); in inno_hdmi_rk3328_phy_pll_recalc_rate()
1093 if ((inno_read(inno, 0xa2) & 0x30) == 0) { in inno_hdmi_rk3328_phy_pll_recalc_rate()
1094 frac = inno_read(inno, 0xd3) | in inno_hdmi_rk3328_phy_pll_recalc_rate()
1095 (inno_read(inno, 0xd2) << 8) | in inno_hdmi_rk3328_phy_pll_recalc_rate()
1096 (inno_read(inno, 0xd1) << 16); in inno_hdmi_rk3328_phy_pll_recalc_rate()
1099 if (inno_read(inno, 0xa0) & 2) { in inno_hdmi_rk3328_phy_pll_recalc_rate()
1102 no_a = inno_read(inno, 0xa5) & 0x1f; in inno_hdmi_rk3328_phy_pll_recalc_rate()
1103 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; in inno_hdmi_rk3328_phy_pll_recalc_rate()
1104 no_d = inno_read(inno, 0xa6) & 0x1f; in inno_hdmi_rk3328_phy_pll_recalc_rate()
1112 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3328_phy_pll_recalc_rate()
1114 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3328_phy_pll_recalc_rate()
1120 inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3528_power_on() argument
1128 inno_update_bits(inno, 0xaa, 1, 0); in inno_hdmi_phy_rk3528_power_on()
1131 inno_write(inno, 0xab, val); in inno_hdmi_phy_rk3528_power_on()
1134 inno_write(inno, 0xad, 0x8); in inno_hdmi_phy_rk3528_power_on()
1135 inno_write(inno, 0xaa, 2); in inno_hdmi_phy_rk3528_power_on()
1138 inno_write(inno, 0xad, val); in inno_hdmi_phy_rk3528_power_on()
1139 inno_write(inno, 0xaa, 0x0e); in inno_hdmi_phy_rk3528_power_on()
1143 inno_write(inno, 0xac, val); in inno_hdmi_phy_rk3528_power_on()
1145 inno_update_bits(inno, 0xad, BIT(4), val); in inno_hdmi_phy_rk3528_power_on()
1149 inno_write(inno, 0xbf, val); in inno_hdmi_phy_rk3528_power_on()
1153 inno_write(inno, 0xc0, val); in inno_hdmi_phy_rk3528_power_on()
1156 inno_write(inno, 0xb5, phy_cfg->regs[2]); in inno_hdmi_phy_rk3528_power_on()
1157 inno_write(inno, 0xb6, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
1158 inno_write(inno, 0xb7, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
1159 inno_write(inno, 0xb8, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
1162 inno_write(inno, 0xbb, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
1163 inno_write(inno, 0xbc, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
1164 inno_write(inno, 0xbd, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
1167 inno_write(inno, 0xb4, 0x7); in inno_hdmi_phy_rk3528_power_on()
1170 inno_write(inno, 0xbe, 0x70); in inno_hdmi_phy_rk3528_power_on()
1172 inno_write(inno, 0xb2, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1175 if (inno_read(inno, 0xaf) & 1) in inno_hdmi_phy_rk3528_power_on()
1179 if (!(inno_read(inno, 0xaf) & 1)) { in inno_hdmi_phy_rk3528_power_on()
1180 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3528_power_on()
1186 inno_write(inno, 0xc7, 0x76); in inno_hdmi_phy_rk3528_power_on()
1187 inno_write(inno, 0xc5, 0x83); in inno_hdmi_phy_rk3528_power_on()
1188 inno_write(inno, 0xc8, 0x00); in inno_hdmi_phy_rk3528_power_on()
1189 inno_write(inno, 0xc9, 0x2f); in inno_hdmi_phy_rk3528_power_on()
1190 inno_write(inno, 0xca, 0x2f); in inno_hdmi_phy_rk3528_power_on()
1191 inno_write(inno, 0xcb, 0x2f); in inno_hdmi_phy_rk3528_power_on()
1193 inno_write(inno, 0xc7, 0x76); in inno_hdmi_phy_rk3528_power_on()
1194 inno_write(inno, 0xc5, 0x83); in inno_hdmi_phy_rk3528_power_on()
1195 inno_write(inno, 0xc8, 0x00); in inno_hdmi_phy_rk3528_power_on()
1196 inno_write(inno, 0xc9, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1197 inno_write(inno, 0xca, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1198 inno_write(inno, 0xcb, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1203 do_div(temp, inno->tmdsclock); in inno_hdmi_phy_rk3528_power_on()
1204 inno_write(inno, 0xd8, (temp >> 8) & 0xff); in inno_hdmi_phy_rk3528_power_on()
1205 inno_write(inno, 0xd9, temp & 0xff); in inno_hdmi_phy_rk3528_power_on()
1208 inno_update_bits(inno, 0xaa, 1, 0); in inno_hdmi_phy_rk3528_power_on()
1210 inno_update_bits(inno, 0xb0, 4, 4); in inno_hdmi_phy_rk3528_power_on()
1211 inno_write(inno, 0xb2, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1216 inno_update_bits(inno, 0x02, 1, 0); in inno_hdmi_phy_rk3528_power_on()
1217 inno_update_bits(inno, 0x02, 1, 1); in inno_hdmi_phy_rk3528_power_on()
1220 inno_write(inno, 0x05, 0x22); in inno_hdmi_phy_rk3528_power_on()
1221 inno_write(inno, 0x07, 0x22); in inno_hdmi_phy_rk3528_power_on()
1222 inno_write(inno, 0xcc, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1227 static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3528_power_off() argument
1230 inno_write(inno, 0xb2, 0); in inno_hdmi_phy_rk3528_power_off()
1232 inno_write(inno, 0xbe, 0); in inno_hdmi_phy_rk3528_power_off()
1234 inno_update_bits(inno, 0xaa, 1, 1); in inno_hdmi_phy_rk3528_power_off()
1236 inno_write(inno, 0xcc, 0); in inno_hdmi_phy_rk3528_power_off()
1238 inno_update_bits(inno, 0xb0, 4, 0); in inno_hdmi_phy_rk3528_power_off()
1240 inno_write(inno, 0x05, 0); in inno_hdmi_phy_rk3528_power_off()
1241 inno_write(inno, 0x07, 0); in inno_hdmi_phy_rk3528_power_off()
1244 static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3528_init() argument
1250 inno_write(inno, 0x02, 0x81); in inno_hdmi_phy_rk3528_init()
1253 if (inno_read(inno, 0xa9) & BIT(0)) { in inno_hdmi_phy_rk3528_init()
1254 dev_info(inno->dev, "phy had been powered up\n"); in inno_hdmi_phy_rk3528_init()
1255 inno->phy->power_count = 1; in inno_hdmi_phy_rk3528_init()
1258 inno_hdmi_phy_rk3528_power_off(inno); in inno_hdmi_phy_rk3528_init()
1263 inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3528_pre_pll_update() argument
1268 inno_update_bits(inno, 0xb0, 4, 4); in inno_hdmi_phy_rk3528_pre_pll_update()
1269 inno_write(inno, 0xcc, 0x0f); in inno_hdmi_phy_rk3528_pre_pll_update()
1272 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1274 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3528_pre_pll_update()
1275 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3528_pre_pll_update()
1280 inno_write(inno, 0xa2, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1281 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3528_pre_pll_update()
1284 inno_write(inno, 0xa5, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1287 inno_write(inno, 0xa6, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1291 inno_write(inno, 0xa4, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1295 inno_write(inno, 0xd3, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1297 inno_write(inno, 0xd2, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1299 inno_write(inno, 0xd1, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1301 inno_write(inno, 0xd3, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1302 inno_write(inno, 0xd2, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1303 inno_write(inno, 0xd1, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1308 if (inno_read(inno, 0xa9) & 1) in inno_hdmi_phy_rk3528_pre_pll_update()
1313 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3528_pre_pll_update()
1321 inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, in inno_hdmi_rk3528_phy_pll_recalc_rate() argument
1329 nd = inno_read(inno, 0xa1) & 0x3f; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1330 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1332 if ((inno_read(inno, 0xa2) & 0x30) == 0) { in inno_hdmi_rk3528_phy_pll_recalc_rate()
1333 frac = inno_read(inno, 0xd3) | in inno_hdmi_rk3528_phy_pll_recalc_rate()
1334 (inno_read(inno, 0xd2) << 8) | in inno_hdmi_rk3528_phy_pll_recalc_rate()
1335 (inno_read(inno, 0xd1) << 16); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1338 if (inno_read(inno, 0xa0) & 2) { in inno_hdmi_rk3528_phy_pll_recalc_rate()
1341 no_a = inno_read(inno, 0xa5) & 0x1f; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1342 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1343 no_d = inno_read(inno, 0xa6) & 0x1f; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1351 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1353 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1359 inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, in inno_hdmi_rk3228_phy_pll_recalc_rate() argument
1366 nd = inno_read(inno, 0xe2) & 0x1f; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1367 nf = ((inno_read(inno, 0xe2) & 0x80) << 1) | inno_read(inno, 0xe3); in inno_hdmi_rk3228_phy_pll_recalc_rate()
1370 if ((inno_read(inno, 0xe2) >> 5) & 0x1) { in inno_hdmi_rk3228_phy_pll_recalc_rate()
1373 no_a = inno_read(inno, 0xe4) & 0x1f; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1376 no_b = ((inno_read(inno, 0xe4) >> 5) & 0x3) + 2; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1377 no_d = inno_read(inno, 0xe5) & 0x1f; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1385 inno->pixclock = vco; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1387 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3228_phy_pll_recalc_rate()
1389 return inno->pixclock; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1456 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, in inno_hdmi_update_phy_table() argument
1487 struct inno_hdmi_phy *inno; in inno_hdmi_phy_probe() local
1495 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); in inno_hdmi_phy_probe()
1496 if (!inno) in inno_hdmi_phy_probe()
1499 inno->dev = dev; in inno_hdmi_phy_probe()
1502 inno->plat_data = (struct inno_hdmi_phy_drv_data *)match->data; in inno_hdmi_phy_probe()
1503 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_probe()
1511 inno->sysclk = devm_clk_get(inno->dev, "sysclk"); in inno_hdmi_phy_probe()
1512 if (IS_ERR(inno->sysclk)) { in inno_hdmi_phy_probe()
1513 ret = PTR_ERR(inno->sysclk); in inno_hdmi_phy_probe()
1514 dev_err(inno->dev, "Unable to get inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1517 ret = clk_prepare_enable(inno->sysclk); in inno_hdmi_phy_probe()
1519 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1523 inno->regmap = devm_regmap_init_mmio(dev, regs, in inno_hdmi_phy_probe()
1525 if (IS_ERR(inno->regmap)) { in inno_hdmi_phy_probe()
1526 ret = PTR_ERR(inno->regmap); in inno_hdmi_phy_probe()
1531 inno->phy = devm_phy_create(dev, NULL, &inno_hdmi_phy_ops); in inno_hdmi_phy_probe()
1532 if (IS_ERR(inno->phy)) { in inno_hdmi_phy_probe()
1534 ret = PTR_ERR(inno->phy); in inno_hdmi_phy_probe()
1554 inno->phy_cfg = devm_kzalloc(dev, val + PHY_TAB_LEN, in inno_hdmi_phy_probe()
1556 if (!inno->phy_cfg) { in inno_hdmi_phy_probe()
1563 ret = inno_hdmi_update_phy_table(inno, phy_config, in inno_hdmi_phy_probe()
1564 inno->phy_cfg, in inno_hdmi_phy_probe()
1575 phy_set_drvdata(inno->phy, inno); in inno_hdmi_phy_probe()
1576 phy_set_bus_width(inno->phy, 8); in inno_hdmi_phy_probe()
1585 if (inno->plat_data->ops->init) in inno_hdmi_phy_probe()
1586 inno->plat_data->ops->init(inno); in inno_hdmi_phy_probe()
1588 ret = inno_hdmi_phy_clk_register(inno); in inno_hdmi_phy_probe()
1592 inno->irq = platform_get_irq(pdev, 0); in inno_hdmi_phy_probe()
1593 if (inno->irq > 0) { in inno_hdmi_phy_probe()
1594 ret = devm_request_threaded_irq(inno->dev, inno->irq, in inno_hdmi_phy_probe()
1597 dev_name(inno->dev), inno); in inno_hdmi_phy_probe()
1601 platform_set_drvdata(pdev, inno); in inno_hdmi_phy_probe()
1607 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_probe()
1613 struct inno_hdmi_phy *inno = platform_get_drvdata(pdev); in inno_hdmi_phy_remove() local
1616 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_remove()