Lines Matching refs:inno
306 static void phy_update_bits(struct inno_dsidphy *inno, in phy_update_bits() argument
312 orig = readl(inno->phy_base + reg); in phy_update_bits()
315 writel(tmp, inno->phy_base + reg); in phy_update_bits()
318 static void host_update_bits(struct inno_dsidphy *inno, in host_update_bits() argument
323 orig = readl(inno->host_base + reg); in host_update_bits()
326 writel(tmp, inno->host_base + reg); in host_update_bits()
329 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, in inno_dsidphy_pll_calc_rate() argument
332 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
391 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
392 inno->pll.fbdiv = best_fbdiv; in inno_dsidphy_pll_calc_rate()
393 inno->pll.rate = best_freq; in inno_dsidphy_pll_calc_rate()
400 inno_mipi_dphy_get_timing(struct inno_dsidphy *inno) in inno_mipi_dphy_get_timing() argument
404 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC; in inno_mipi_dphy_get_timing()
407 timings = inno->pdata->inno_mipi_dphy_timing_table; in inno_mipi_dphy_get_timing()
408 num_timings = inno->pdata->num_timings; in inno_mipi_dphy_get_timing()
420 static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_dsidphy *inno) in inno_mipi_dphy_max_2_5GHz_pll_enable() argument
423 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
424 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
426 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_2_5GHz_pll_enable()
428 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_mipi_dphy_max_2_5GHz_pll_enable()
431 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, in inno_mipi_dphy_max_2_5GHz_pll_enable()
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_2_5GHz_pll_enable()
439 static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_dsidphy *inno) in inno_mipi_dphy_max_1GHz_pll_enable() argument
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
443 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_max_1GHz_pll_enable()
444 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
445 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); in inno_mipi_dphy_max_1GHz_pll_enable()
446 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_1GHz_pll_enable()
447 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_1GHz_pll_enable()
449 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_1GHz_pll_enable()
454 static void inno_mipi_dphy_reset(struct inno_dsidphy *inno) in inno_mipi_dphy_reset() argument
457 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
460 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
463 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_mipi_dphy_reset()
466 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_mipi_dphy_reset()
470 static void inno_mipi_dphy_timing_init(struct inno_dsidphy *inno) in inno_mipi_dphy_timing_init() argument
472 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; in inno_mipi_dphy_timing_init()
480 txbyteclkhs = inno->pll.rate / 8; in inno_mipi_dphy_timing_init()
521 timing = inno_mipi_dphy_get_timing(inno); in inno_mipi_dphy_timing_init()
526 if (inno->pdata->max_rate == MAX_1GHZ) { in inno_mipi_dphy_timing_init()
545 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, in inno_mipi_dphy_timing_init()
547 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, in inno_mipi_dphy_timing_init()
550 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_mipi_dphy_timing_init()
551 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK, in inno_mipi_dphy_timing_init()
554 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
556 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, in inno_mipi_dphy_timing_init()
559 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_mipi_dphy_timing_init()
560 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK, in inno_mipi_dphy_timing_init()
563 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
566 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_mipi_dphy_timing_init()
567 phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK, in inno_mipi_dphy_timing_init()
570 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
572 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, in inno_mipi_dphy_timing_init()
574 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, in inno_mipi_dphy_timing_init()
576 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
578 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, in inno_mipi_dphy_timing_init()
580 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, in inno_mipi_dphy_timing_init()
582 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, in inno_mipi_dphy_timing_init()
587 static void inno_mipi_dphy_lane_enable(struct inno_dsidphy *inno) in inno_mipi_dphy_lane_enable() argument
591 switch (inno->lanes) { in inno_mipi_dphy_lane_enable()
607 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val); in inno_mipi_dphy_lane_enable()
610 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) in inno_dsidphy_mipi_mode_enable() argument
613 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_dsidphy_mipi_mode_enable()
617 if (inno->pdata->soc_type == PX30S) in inno_dsidphy_mipi_mode_enable()
618 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01, in inno_dsidphy_mipi_mode_enable()
621 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
622 inno_mipi_dphy_max_2_5GHz_pll_enable(inno); in inno_dsidphy_mipi_mode_enable()
624 inno_mipi_dphy_max_1GHz_pll_enable(inno); in inno_dsidphy_mipi_mode_enable()
626 inno_mipi_dphy_reset(inno); in inno_dsidphy_mipi_mode_enable()
627 inno_mipi_dphy_timing_init(inno); in inno_dsidphy_mipi_mode_enable()
628 inno_mipi_dphy_lane_enable(inno); in inno_dsidphy_mipi_mode_enable()
629 inno_mipi_dphy_lane_enable(inno); in inno_dsidphy_mipi_mode_enable()
632 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) in inno_dsidphy_lvds_mode_enable() argument
638 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_dsidphy_lvds_mode_enable()
644 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_lvds_mode_enable()
648 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_lvds_mode_enable()
653 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_dsidphy_lvds_mode_enable()
656 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_dsidphy_lvds_mode_enable()
658 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_dsidphy_lvds_mode_enable()
660 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_dsidphy_lvds_mode_enable()
662 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); in inno_dsidphy_lvds_mode_enable()
664 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_lvds_mode_enable()
671 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e, in inno_dsidphy_lvds_mode_enable()
675 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_dsidphy_lvds_mode_enable()
679 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_lvds_mode_enable()
685 static void inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy *inno) in inno_dsidphy_phy_ttl_mode_enable() argument
688 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_phy_ttl_mode_enable()
692 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_phy_ttl_mode_enable()
697 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_dsidphy_phy_ttl_mode_enable()
701 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_dsidphy_phy_ttl_mode_enable()
705 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_phy_ttl_mode_enable()
710 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); in inno_dsidphy_phy_ttl_mode_enable()
715 struct inno_dsidphy *inno = phy_get_drvdata(phy); in inno_dsidphy_power_on() local
718 clk_prepare_enable(inno->pclk_phy); in inno_dsidphy_power_on()
719 clk_prepare_enable(inno->ref_clk); in inno_dsidphy_power_on()
720 pm_runtime_get_sync(inno->dev); in inno_dsidphy_power_on()
723 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_dsidphy_power_on()
726 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_dsidphy_power_on()
731 inno_dsidphy_mipi_mode_enable(inno); in inno_dsidphy_power_on()
734 inno_dsidphy_lvds_mode_enable(inno); in inno_dsidphy_power_on()
737 inno_dsidphy_phy_ttl_mode_enable(inno); in inno_dsidphy_power_on()
745 struct inno_dsidphy *inno = phy_get_drvdata(phy); in inno_dsidphy_power_off() local
747 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); in inno_dsidphy_power_off()
748 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_dsidphy_power_off()
751 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_dsidphy_power_off()
753 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_dsidphy_power_off()
756 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); in inno_dsidphy_power_off()
757 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_dsidphy_power_off()
760 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_power_off()
764 pm_runtime_put(inno->dev); in inno_dsidphy_power_off()
765 clk_disable_unprepare(inno->ref_clk); in inno_dsidphy_power_off()
766 clk_disable_unprepare(inno->pclk_phy); in inno_dsidphy_power_off()
780 struct inno_dsidphy *inno = phy_get_drvdata(phy); in inno_dsidphy_configure() local
781 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; in inno_dsidphy_configure()
792 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg)); in inno_dsidphy_configure()
794 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate); in inno_dsidphy_configure()
795 cfg->hs_clk_rate = inno->pll.rate; in inno_dsidphy_configure()
796 opts->mipi_dphy.hs_clk_rate = inno->pll.rate; in inno_dsidphy_configure()
803 struct inno_dsidphy *inno = phy_get_drvdata(phy); in inno_dsidphy_init() local
805 clk_prepare_enable(inno->pclk_phy); in inno_dsidphy_init()
806 clk_prepare_enable(inno->ref_clk); in inno_dsidphy_init()
807 pm_runtime_get_sync(inno->dev); in inno_dsidphy_init()
814 struct inno_dsidphy *inno = phy_get_drvdata(phy); in inno_dsidphy_exit() local
816 pm_runtime_put(inno->dev); in inno_dsidphy_exit()
817 clk_disable_unprepare(inno->ref_clk); in inno_dsidphy_exit()
818 clk_disable_unprepare(inno->pclk_phy); in inno_dsidphy_exit()
885 struct inno_dsidphy *inno; in inno_dsidphy_probe() local
891 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); in inno_dsidphy_probe()
892 if (!inno) in inno_dsidphy_probe()
895 inno->dev = dev; in inno_dsidphy_probe()
896 inno->pdata = of_device_get_match_data(inno->dev); in inno_dsidphy_probe()
898 inno->pdata = &px30s_video_phy_plat_data; in inno_dsidphy_probe()
900 platform_set_drvdata(pdev, inno); in inno_dsidphy_probe()
902 inno->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy"); in inno_dsidphy_probe()
903 if (IS_ERR(inno->phy_base)) in inno_dsidphy_probe()
904 return PTR_ERR(inno->phy_base); in inno_dsidphy_probe()
912 inno->host_base = devm_ioremap(dev, res->start, resource_size(res)); in inno_dsidphy_probe()
913 if (IS_ERR(inno->host_base)) in inno_dsidphy_probe()
914 return PTR_ERR(inno->host_base); in inno_dsidphy_probe()
916 inno->ref_clk = devm_clk_get(dev, "ref"); in inno_dsidphy_probe()
917 if (IS_ERR(inno->ref_clk)) { in inno_dsidphy_probe()
918 ret = PTR_ERR(inno->ref_clk); in inno_dsidphy_probe()
923 inno->pclk_phy = devm_clk_get(dev, "pclk"); in inno_dsidphy_probe()
924 if (IS_ERR(inno->pclk_phy)) { in inno_dsidphy_probe()
925 ret = PTR_ERR(inno->pclk_phy); in inno_dsidphy_probe()
930 inno->pclk_host = devm_clk_get(dev, "pclk_host"); in inno_dsidphy_probe()
931 if (IS_ERR(inno->pclk_host)) { in inno_dsidphy_probe()
932 ret = PTR_ERR(inno->pclk_host); in inno_dsidphy_probe()
937 inno->rst = devm_reset_control_get(dev, "apb"); in inno_dsidphy_probe()
938 if (IS_ERR(inno->rst)) { in inno_dsidphy_probe()
939 ret = PTR_ERR(inno->rst); in inno_dsidphy_probe()
951 if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes)) in inno_dsidphy_probe()
952 inno->lanes = 4; in inno_dsidphy_probe()
954 phy_set_drvdata(phy, inno); in inno_dsidphy_probe()
970 struct inno_dsidphy *inno = platform_get_drvdata(pdev); in inno_dsidphy_remove() local
972 pm_runtime_disable(inno->dev); in inno_dsidphy_remove()