Lines Matching refs:REGISTER_PART_LVDS
260 REGISTER_PART_LVDS, enumerator
613 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_dsidphy_mipi_mode_enable()
644 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_lvds_mode_enable()
648 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_lvds_mode_enable()
653 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_dsidphy_lvds_mode_enable()
662 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); in inno_dsidphy_lvds_mode_enable()
664 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_lvds_mode_enable()
675 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_dsidphy_lvds_mode_enable()
679 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_lvds_mode_enable()
688 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_phy_ttl_mode_enable()
692 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_dsidphy_phy_ttl_mode_enable()
697 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_dsidphy_phy_ttl_mode_enable()
701 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_dsidphy_phy_ttl_mode_enable()
705 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_phy_ttl_mode_enable()
756 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); in inno_dsidphy_power_off()
757 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_dsidphy_power_off()
760 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_dsidphy_power_off()