Lines Matching full:efuse
3 * Rockchip eFuse Driver
111 /* setup efuse timing */ in rk1808_efuse_timing_init()
130 /* clear efuse timing */ in rk1808_efuse_timing_deinit()
146 struct rockchip_efuse_chip *efuse = context; in rockchip_rk1808_efuse_read() local
152 mutex_lock(&efuse->mutex); in rockchip_rk1808_efuse_read()
154 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk1808_efuse_read()
156 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk1808_efuse_read()
171 rk1808_efuse_timing_init(efuse->base); in rockchip_rk1808_efuse_read()
176 efuse->base + RK1808_AUTO_CTRL); in rockchip_rk1808_efuse_read()
178 status = readl(efuse->base + RK1808_INT_STATUS); in rockchip_rk1808_efuse_read()
183 out_value = readl(efuse->base + RK1808_DOUT); in rockchip_rk1808_efuse_read()
184 writel(RK1808_INT_FINISH, efuse->base + RK1808_INT_STATUS); in rockchip_rk1808_efuse_read()
191 rk1808_efuse_timing_deinit(efuse->base); in rockchip_rk1808_efuse_read()
194 rk1808_efuse_timing_deinit(efuse->base); in rockchip_rk1808_efuse_read()
195 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk1808_efuse_read()
197 mutex_unlock(&efuse->mutex); in rockchip_rk1808_efuse_read()
205 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3128_efuse_read() local
209 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk3128_efuse_read()
211 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3128_efuse_read()
215 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
218 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3128_efuse_read()
220 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
221 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3128_efuse_read()
223 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
225 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3128_efuse_read()
226 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
228 *buf++ = readb(efuse->base + REG_EFUSE_DOUT); in rockchip_rk3128_efuse_read()
229 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3128_efuse_read()
230 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
235 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
237 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk3128_efuse_read()
245 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_read() local
249 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk3288_efuse_read()
251 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
255 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
258 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
260 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
261 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
263 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
265 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
266 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
268 *buf++ = readb(efuse->base + REG_EFUSE_DOUT); in rockchip_rk3288_efuse_read()
269 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
270 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
275 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
277 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk3288_efuse_read()
286 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_secure_read() local
291 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk3288_efuse_secure_read()
293 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_secure_read()
297 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, in rockchip_rk3288_efuse_secure_read()
301 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_secure_read()
303 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3288_efuse_secure_read()
304 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_secure_read()
306 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3288_efuse_secure_read()
308 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_secure_read()
310 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3288_efuse_secure_read()
312 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT); in rockchip_rk3288_efuse_secure_read()
313 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_secure_read()
315 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3288_efuse_secure_read()
320 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, in rockchip_rk3288_efuse_secure_read()
323 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk3288_efuse_secure_read()
331 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3328_efuse_read() local
337 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk3328_efuse_read()
339 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3328_efuse_read()
343 /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */ in rockchip_rk3328_efuse_read()
360 efuse->base + RK3328_AUTO_CTRL); in rockchip_rk3328_efuse_read()
362 status = readl(efuse->base + RK3328_INT_STATUS); in rockchip_rk3328_efuse_read()
367 out_value = readl(efuse->base + RK3328_DOUT); in rockchip_rk3328_efuse_read()
368 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS); in rockchip_rk3328_efuse_read()
378 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk3328_efuse_read()
386 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3368_efuse_read() local
391 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk3368_efuse_read()
393 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3368_efuse_read()
397 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, in rockchip_rk3368_efuse_read()
401 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & in rockchip_rk3368_efuse_read()
403 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3368_efuse_read()
404 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | in rockchip_rk3368_efuse_read()
406 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3368_efuse_read()
408 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | in rockchip_rk3368_efuse_read()
410 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3368_efuse_read()
412 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT); in rockchip_rk3368_efuse_read()
413 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & in rockchip_rk3368_efuse_read()
415 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val); in rockchip_rk3368_efuse_read()
420 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, in rockchip_rk3368_efuse_read()
423 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk3368_efuse_read()
431 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3399_efuse_read() local
437 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks); in rockchip_rk3399_efuse_read()
439 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3399_efuse_read()
456 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3399_efuse_read()
459 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | in rockchip_rk3399_efuse_read()
461 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3399_efuse_read()
463 out_value = readl(efuse->base + REG_EFUSE_DOUT); in rockchip_rk3399_efuse_read()
464 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), in rockchip_rk3399_efuse_read()
465 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3399_efuse_read()
473 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3399_efuse_read()
480 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks); in rockchip_rk3399_efuse_read()
486 .name = "rockchip-efuse",
495 .compatible = "rockchip,rk1808-efuse",
499 .compatible = "rockchip,rockchip-efuse",
503 .compatible = "rockchip,rk3066a-efuse",
507 .compatible = "rockchip,rk3128-efuse",
511 .compatible = "rockchip,rk3188-efuse",
515 .compatible = "rockchip,rk3228-efuse",
519 .compatible = "rockchip,rk3288-efuse",
523 .compatible = "rockchip,rk3288-secure-efuse",
527 .compatible = "rockchip,rk3328-efuse",
531 .compatible = "rockchip,rk3368-efuse",
535 .compatible = "rockchip,rk3399-efuse",
546 struct rockchip_efuse_chip *efuse; in rockchip_efuse_probe() local
556 efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip), in rockchip_efuse_probe()
558 if (!efuse) in rockchip_efuse_probe()
562 efuse->phys = res->start; in rockchip_efuse_probe()
563 efuse->base = devm_ioremap_resource(dev, res); in rockchip_efuse_probe()
564 if (IS_ERR(efuse->base)) in rockchip_efuse_probe()
565 return PTR_ERR(efuse->base); in rockchip_efuse_probe()
567 efuse->num_clks = devm_clk_bulk_get_all(dev, &efuse->clks); in rockchip_efuse_probe()
568 if (efuse->num_clks < 1) in rockchip_efuse_probe()
571 mutex_init(&efuse->mutex); in rockchip_efuse_probe()
573 efuse->dev = dev; in rockchip_efuse_probe()
574 if (of_property_read_u32(dev->of_node, "rockchip,efuse-size", in rockchip_efuse_probe()
578 econfig.priv = efuse; in rockchip_efuse_probe()
579 econfig.dev = efuse->dev; in rockchip_efuse_probe()
588 .name = "rockchip-efuse",
599 pr_err("failed to register efuse driver\n"); in rockchip_efuse_init()