Lines Matching +full:ciu +full:- +full:drive
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
17 #include "dw_mmc-pltfm.h"
33 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
38 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
45 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
48 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
50 if (ios->clock < priv->f_min) { in dw_mci_rk3288_set_ios()
51 ios->clock = priv->f_min; in dw_mci_rk3288_set_ios()
52 host->slot->clock = ios->clock; in dw_mci_rk3288_set_ios()
55 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
56 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
57 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
59 cclkin = ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
61 ret = clk_set_rate(host->ciu_clk, cclkin); in dw_mci_rk3288_set_ios()
63 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); in dw_mci_rk3288_set_ios()
65 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
66 if (bus_hz != host->bus_hz) { in dw_mci_rk3288_set_ios()
67 host->bus_hz = bus_hz; in dw_mci_rk3288_set_ios()
69 host->current_speed = 0; in dw_mci_rk3288_set_ios()
73 if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS) in dw_mci_rk3288_set_ios()
74 clk_set_phase(priv->sample_clk, priv->default_sample_phase); in dw_mci_rk3288_set_ios()
77 * Set the drive phase offset based on speed mode to achieve hold times. in dw_mci_rk3288_set_ios()
102 if (!IS_ERR(priv->drv_clk)) { in dw_mci_rk3288_set_ios()
113 switch (ios->timing) { in dw_mci_rk3288_set_ios()
120 if (ios->bus_width == MMC_BUS_WIDTH_8) in dw_mci_rk3288_set_ios()
137 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
146 struct dw_mci *host = slot->host; in dw_mci_v2_execute_tuning()
147 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_v2_execute_tuning()
148 struct mmc_host *mmc = slot->mmc; in dw_mci_v2_execute_tuning()
155 i = clk_get_phase(priv->sample_clk) / 90; in dw_mci_v2_execute_tuning()
169 degree = degrees[i] + priv->last_degree + 90; in dw_mci_v2_execute_tuning()
171 clk_set_phase(priv->sample_clk, degree); in dw_mci_v2_execute_tuning()
178 … dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree); in dw_mci_v2_execute_tuning()
180 clk_set_phase(priv->sample_clk, degree); in dw_mci_v2_execute_tuning()
188 dev_warn(host->dev, "All phases bad!"); in dw_mci_v2_execute_tuning()
189 return -EIO; in dw_mci_v2_execute_tuning()
193 dev_info(host->dev, "Successfully tuned phase to %d\n", degree); in dw_mci_v2_execute_tuning()
194 priv->last_degree = degree; in dw_mci_v2_execute_tuning()
200 struct dw_mci *host = slot->host; in dw_mci_rk3288_execute_tuning()
201 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_execute_tuning()
202 struct mmc_host *mmc = slot->mmc; in dw_mci_rk3288_execute_tuning()
212 int longest_range_len = -1; in dw_mci_rk3288_execute_tuning()
213 int longest_range = -1; in dw_mci_rk3288_execute_tuning()
216 if (IS_ERR(priv->sample_clk)) { in dw_mci_rk3288_execute_tuning()
217 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); in dw_mci_rk3288_execute_tuning()
218 return -EIO; in dw_mci_rk3288_execute_tuning()
221 if (priv->use_v2_tuning) { in dw_mci_rk3288_execute_tuning()
228 ranges = kmalloc_array(priv->num_phases / 2 + 1, in dw_mci_rk3288_execute_tuning()
231 return -ENOMEM; in dw_mci_rk3288_execute_tuning()
234 for (i = 0; i < priv->num_phases; ) { in dw_mci_rk3288_execute_tuning()
236 if (TUNING_ITERATION_TO_PHASE(i, priv->num_phases) > 270) in dw_mci_rk3288_execute_tuning()
238 clk_set_phase(priv->sample_clk, in dw_mci_rk3288_execute_tuning()
239 TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); in dw_mci_rk3288_execute_tuning()
248 ranges[range_count-1].start = i; in dw_mci_rk3288_execute_tuning()
251 ranges[range_count-1].end = i; in dw_mci_rk3288_execute_tuning()
253 } else if (i == priv->num_phases - 1) { in dw_mci_rk3288_execute_tuning()
262 i += DIV_ROUND_UP(20 * priv->num_phases, 360); in dw_mci_rk3288_execute_tuning()
265 if (i >= priv->num_phases) in dw_mci_rk3288_execute_tuning()
266 i = priv->num_phases - 1; in dw_mci_rk3288_execute_tuning()
273 dev_warn(host->dev, "All phases bad!"); in dw_mci_rk3288_execute_tuning()
274 ret = -EIO; in dw_mci_rk3288_execute_tuning()
280 ranges[0].start = ranges[range_count-1].start; in dw_mci_rk3288_execute_tuning()
281 range_count--; in dw_mci_rk3288_execute_tuning()
284 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { in dw_mci_rk3288_execute_tuning()
285 clk_set_phase(priv->sample_clk, priv->default_sample_phase); in dw_mci_rk3288_execute_tuning()
286 dev_info(host->dev, "All phases work, using default phase %d.", in dw_mci_rk3288_execute_tuning()
287 priv->default_sample_phase); in dw_mci_rk3288_execute_tuning()
293 int len = (ranges[i].end - ranges[i].start + 1); in dw_mci_rk3288_execute_tuning()
296 len += priv->num_phases; in dw_mci_rk3288_execute_tuning()
303 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", in dw_mci_rk3288_execute_tuning()
305 priv->num_phases), in dw_mci_rk3288_execute_tuning()
307 priv->num_phases), in dw_mci_rk3288_execute_tuning()
312 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", in dw_mci_rk3288_execute_tuning()
314 priv->num_phases), in dw_mci_rk3288_execute_tuning()
316 priv->num_phases), in dw_mci_rk3288_execute_tuning()
321 middle_phase %= priv->num_phases; in dw_mci_rk3288_execute_tuning()
322 real_middle_phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases); in dw_mci_rk3288_execute_tuning()
342 dev_info(host->dev, "Successfully tuned phase to %d\n", in dw_mci_rk3288_execute_tuning()
345 clk_set_phase(priv->sample_clk, real_middle_phase); in dw_mci_rk3288_execute_tuning()
354 struct device_node *np = host->dev->of_node; in dw_mci_rk3288_parse_dt()
357 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); in dw_mci_rk3288_parse_dt()
359 return -ENOMEM; in dw_mci_rk3288_parse_dt()
366 if (of_device_is_compatible(host->dev->of_node, in dw_mci_rk3288_parse_dt()
367 "rockchip,rk3568-dw-mshc")) in dw_mci_rk3288_parse_dt()
368 priv->f_min = 375000; in dw_mci_rk3288_parse_dt()
370 priv->f_min = 100000; in dw_mci_rk3288_parse_dt()
372 if (of_property_read_u32(np, "rockchip,desired-num-phases", in dw_mci_rk3288_parse_dt()
373 &priv->num_phases)) in dw_mci_rk3288_parse_dt()
374 priv->num_phases = 360; in dw_mci_rk3288_parse_dt()
376 if (of_property_read_u32(np, "rockchip,default-sample-phase", in dw_mci_rk3288_parse_dt()
377 &priv->default_sample_phase)) in dw_mci_rk3288_parse_dt()
378 priv->default_sample_phase = 0; in dw_mci_rk3288_parse_dt()
380 if (of_property_read_bool(np, "rockchip,use-v2-tuning")) in dw_mci_rk3288_parse_dt()
381 priv->use_v2_tuning = true; in dw_mci_rk3288_parse_dt()
383 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); in dw_mci_rk3288_parse_dt()
384 if (IS_ERR(priv->drv_clk)) in dw_mci_rk3288_parse_dt()
385 dev_dbg(host->dev, "ciu-drive not available\n"); in dw_mci_rk3288_parse_dt()
387 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); in dw_mci_rk3288_parse_dt()
388 if (IS_ERR(priv->sample_clk)) in dw_mci_rk3288_parse_dt()
389 dev_dbg(host->dev, "ciu-sample not available\n"); in dw_mci_rk3288_parse_dt()
391 host->priv = priv; in dw_mci_rk3288_parse_dt()
399 host->sdio_id0 = 8; in dw_mci_rockchip_init()
401 if (of_device_is_compatible(host->dev->of_node, in dw_mci_rockchip_init()
402 "rockchip,rk3288-dw-mshc")) in dw_mci_rockchip_init()
403 host->bus_hz /= RK3288_CLKGEN_DIV; in dw_mci_rockchip_init()
405 if (of_device_is_compatible(host->dev->of_node, in dw_mci_rockchip_init()
406 "rockchip,rv1106-dw-mshc") && in dw_mci_rockchip_init()
408 !strcmp(dev_name(host->dev), "ffaa0000.mmc")) { in dw_mci_rockchip_init()
409 if (device_property_read_bool(host->dev, "no-sd")) { in dw_mci_rockchip_init()
410 dev_err(host->dev, "Invalid usage, should be SD card only\n"); in dw_mci_rockchip_init()
411 return -EINVAL; in dw_mci_rockchip_init()
414 host->is_rv1106_sd = true; in dw_mci_rockchip_init()
415 dev_info(host->dev, "is rv1106 sd\n"); in dw_mci_rockchip_init()
418 host->need_xfer_timer = true; in dw_mci_rockchip_init()
444 { .compatible = "rockchip,rk2928-dw-mshc",
446 { .compatible = "rockchip,rk3288-dw-mshc",
459 if (!pdev->dev.of_node) in dw_mci_rockchip_probe()
460 return -ENODEV; in dw_mci_rockchip_probe()
462 if ((!device_property_read_bool(&pdev->dev, "non-removable") && in dw_mci_rockchip_probe()
463 !device_property_read_bool(&pdev->dev, "cd-gpios")) || in dw_mci_rockchip_probe()
464 (device_property_read_bool(&pdev->dev, "no-sd") && in dw_mci_rockchip_probe()
465 device_property_read_bool(&pdev->dev, "no-mmc"))) in dw_mci_rockchip_probe()
468 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); in dw_mci_rockchip_probe()
469 drv_data = match->data; in dw_mci_rockchip_probe()
475 pm_runtime_get_noresume(&pdev->dev); in dw_mci_rockchip_probe()
476 pm_runtime_set_active(&pdev->dev); in dw_mci_rockchip_probe()
479 pm_runtime_enable(&pdev->dev); in dw_mci_rockchip_probe()
480 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in dw_mci_rockchip_probe()
481 pm_runtime_use_autosuspend(&pdev->dev); in dw_mci_rockchip_probe()
487 pm_runtime_disable(&pdev->dev); in dw_mci_rockchip_probe()
488 pm_runtime_set_suspended(&pdev->dev); in dw_mci_rockchip_probe()
490 pm_runtime_put_noidle(&pdev->dev); in dw_mci_rockchip_probe()
495 pm_runtime_put_autosuspend(&pdev->dev); in dw_mci_rockchip_probe()
502 pm_runtime_get_sync(&pdev->dev); in dw_mci_rockchip_remove()
503 pm_runtime_disable(&pdev->dev); in dw_mci_rockchip_remove()
504 pm_runtime_put_noidle(&pdev->dev); in dw_mci_rockchip_remove()
530 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
531 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");