33 static inline int dsi_write(struct rk628 *rk628, int id, u32 reg, u32 val)  in dsi_write()  argument
39 	return rk628_i2c_write(rk628, dsi_base + reg, val);  in dsi_write()
42 static inline int dsi_read(struct rk628 *rk628, int id, u32 reg, u32 *val)  in dsi_read()  argument
48 	return rk628_i2c_read(rk628, dsi_base + reg, val);  in dsi_read()
51 static inline int dsi_update_bits(struct rk628 *rk628, int id,  in dsi_update_bits()  argument
58 	return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val);  in dsi_update_bits()
67 	struct rk628 *rk628 = dsi->rk628;  in mipi_dphy_power_on_dsi()  local
72 	dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);  in mipi_dphy_power_on_dsi()
73 	dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);  in mipi_dphy_power_on_dsi()
74 	dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, 0);  in mipi_dphy_power_on_dsi()
75 	testif_testclr_assert(dsi->rk628);  in mipi_dphy_power_on_dsi()
78 	rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,  in mipi_dphy_power_on_dsi()
83 	testif_testclr_deassert(dsi->rk628);  in mipi_dphy_power_on_dsi()
85 	mipi_dphy_init_hsfreqrange(dsi->rk628, dsi->lane_mbps);  in mipi_dphy_power_on_dsi()
87 	dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,  in mipi_dphy_power_on_dsi()
89 	dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,  in mipi_dphy_power_on_dsi()
91 	dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);  in mipi_dphy_power_on_dsi()
94 	rk628_txphy_power_on(rk628);  in mipi_dphy_power_on_dsi()
96 	ret = regmap_read_poll_timeout(rk628->regmap[dev_id],  in mipi_dphy_power_on_dsi()
100 		dev_err(rk628->dev, "PHY is not locked\n");  in mipi_dphy_power_on_dsi()
105 	ret = regmap_read_poll_timeout(rk628->regmap[dev_id],  in mipi_dphy_power_on_dsi()
110 		dev_err(rk628->dev, "lane module is not in stop state\n");  in mipi_dphy_power_on_dsi()
118 	struct rk628 *rk628 = dsi->rk628;  in rk628_dsi_pre_enable()  local
121 	dsi_write(rk628, 0, DSI_PWR_UP, RESET);  in rk628_dsi_pre_enable()
122 	dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));  in rk628_dsi_pre_enable()
125 	dsi_write(rk628, 0, DSI_CLKMGR_CFG,  in rk628_dsi_pre_enable()
132 	dsi_write(rk628, 0, DSI_PCKHDL_CFG, val);  in rk628_dsi_pre_enable()
134 	dsi_write(rk628, 0, DSI_TO_CNT_CFG,  in rk628_dsi_pre_enable()
136 	dsi_write(rk628, 0, DSI_BTA_TO_CNT, 0xd00);  in rk628_dsi_pre_enable()
137 	dsi_write(rk628, 0, DSI_PHY_TMR_CFG,  in rk628_dsi_pre_enable()
140 	dsi_write(rk628, 0, DSI_PHY_TMR_LPCLK_CFG,  in rk628_dsi_pre_enable()
142 	dsi_write(rk628, 0, DSI_PHY_IF_CFG,  in rk628_dsi_pre_enable()
147 	dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);  in rk628_dsi_pre_enable()
159 	struct rk628 *rk628 = dsi->rk628;  in rk628_dsi_set_vid_mode()  local
179 	dsi_write(rk628, 0, DSI_VID_MODE_CFG, val);  in rk628_dsi_set_vid_mode()
182 		dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,  in rk628_dsi_set_vid_mode()
188 	dsi_write(rk628, 0, DSI_VID_PKT_SIZE, pkt_size);  in rk628_dsi_set_vid_mode()
198 	dev_info(dsi->rk628->dev, "h: %d %d %d %d, v:%d %d %d %d clock:%llu\n",  in rk628_dsi_set_vid_mode()
205 	dsi_write(rk628, 0, DSI_VID_HLINE_TIME,  in rk628_dsi_set_vid_mode()
209 	dsi_write(rk628, 0, DSI_VID_HSA_TIME, VID_HSA_TIME(hs_time));  in rk628_dsi_set_vid_mode()
212 	dsi_write(rk628, 0, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));  in rk628_dsi_set_vid_mode()
214 	dsi_write(rk628, 0, DSI_VID_VACTIVE_LINES, vactive);  in rk628_dsi_set_vid_mode()
215 	dsi_write(rk628, 0, DSI_VID_VSA_LINES, vs);  in rk628_dsi_set_vid_mode()
216 	dsi_write(rk628, 0, DSI_VID_VFP_LINES, vfp);  in rk628_dsi_set_vid_mode()
217 	dsi_write(rk628, 0, DSI_VID_VBP_LINES, vbp);  in rk628_dsi_set_vid_mode()
219 	dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));  in rk628_dsi_set_vid_mode()
224 	struct rk628 *rk628 = dsi->rk628;  in rk628_dsi_set_cmd_mode()  local
226 	dsi_update_bits(rk628, 0, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);  in rk628_dsi_set_cmd_mode()
227 	dsi_write(rk628, 0, DSI_EDPI_CMD_SIZE,  in rk628_dsi_set_cmd_mode()
229 	dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));  in rk628_dsi_set_cmd_mode()
235 	struct rk628 *rk628 = dsi->rk628;  in rk628_dsi_enable()  local
237 	dsi_write(rk628, 0, DSI_PWR_UP, RESET);  in rk628_dsi_enable()
241 	dsi_write(rk628, 0, DSI_DPI_COLOR_CODING, val);  in rk628_dsi_enable()
252 	dsi_write(rk628, 0, DSI_DPI_CFG_POL, val);  in rk628_dsi_enable()
254 	dsi_write(rk628, 0, DSI_DPI_VCID, DPI_VID(0));  in rk628_dsi_enable()
255 	dsi_write(rk628, 0, DSI_DPI_LP_CMD_TIM,  in rk628_dsi_enable()
257 	dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,  in rk628_dsi_enable()
265 	dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);  in rk628_dsi_enable()
290 	struct rk628 *rk628 = dsi->rk628;  in rk628_mipi_dsi_power_on()  local
294 	rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,  in rk628_mipi_dsi_power_on()
296 	rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN, 0);  in rk628_mipi_dsi_power_on()
300 	rk628_txphy_set_bus_width(dsi->rk628, bus_width);  in rk628_mipi_dsi_power_on()
301 	rk628_txphy_set_mode(dsi->rk628, PHY_MODE_VIDEO_MIPI);  in rk628_mipi_dsi_power_on()
302 	dsi->lane_mbps = rk628_txphy_get_bus_width(dsi->rk628);  in rk628_mipi_dsi_power_on()
303 	dev_dbg(dsi->rk628->dev, "%s mipi bitrate:%llu mbps\n", __func__,  in rk628_mipi_dsi_power_on()