Lines Matching refs:I2C_DEV_DES
104 I2C_DEV_DES = 0, enumerator
214 { I2C_DEV_DES, 2, 0x0006, 0xf0, 0x00, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled
216 { I2C_DEV_DES, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled
218 { I2C_DEV_DES, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range
220 { I2C_DEV_DES, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain
221 { I2C_DEV_DES, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain
222 { I2C_DEV_DES, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain
223 { I2C_DEV_DES, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain
225 { I2C_DEV_DES, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC
226 { I2C_DEV_DES, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC
227 { I2C_DEV_DES, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC
228 { I2C_DEV_DES, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC
230 …{ I2C_DEV_DES, 2, 0x00F0, 0x62, 0x00, 0x00 }, // Phy A -> Pipe Z -> Pipe 0; Phy B -> Pipe Z -> Pip…
231 …{ I2C_DEV_DES, 2, 0x00F1, 0xea, 0x00, 0x00 }, // Phy C -> Pipe Z -> Pipe 2; Phy D -> Pipe Z -> Pip…
232 { I2C_DEV_DES, 2, 0x00F4, 0x0f, 0x00, 0x00 }, // Enable all 4 Pipes
234 { I2C_DEV_DES, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
235 { I2C_DEV_DES, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
237 { I2C_DEV_DES, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
238 { I2C_DEV_DES, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit
239 { I2C_DEV_DES, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
240 { I2C_DEV_DES, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start
241 { I2C_DEV_DES, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
242 { I2C_DEV_DES, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End
244 { I2C_DEV_DES, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
245 { I2C_DEV_DES, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
247 { I2C_DEV_DES, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
248 { I2C_DEV_DES, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit
249 { I2C_DEV_DES, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
250 { I2C_DEV_DES, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start
251 { I2C_DEV_DES, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
252 { I2C_DEV_DES, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End
254 { I2C_DEV_DES, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
255 { I2C_DEV_DES, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
257 { I2C_DEV_DES, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
258 { I2C_DEV_DES, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit
259 { I2C_DEV_DES, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
260 { I2C_DEV_DES, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start
261 { I2C_DEV_DES, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
262 { I2C_DEV_DES, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End
264 { I2C_DEV_DES, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
265 { I2C_DEV_DES, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
267 { I2C_DEV_DES, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
268 { I2C_DEV_DES, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit
269 { I2C_DEV_DES, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
270 { I2C_DEV_DES, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start
271 { I2C_DEV_DES, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
272 { I2C_DEV_DES, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End
274 { I2C_DEV_DES, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode
276 { I2C_DEV_DES, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0
278 { I2C_DEV_DES, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC
279 { I2C_DEV_DES, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC
281 { I2C_DEV_DES, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns
283 { I2C_DEV_DES, 2, 0x040B, 0x80, 0x00, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
284 { I2C_DEV_DES, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit
285 { I2C_DEV_DES, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit
286 { I2C_DEV_DES, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
287 { I2C_DEV_DES, 2, 0x0411, 0x90, 0x00, 0x00 }, // pipe 1 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
288 …{ I2C_DEV_DES, 2, 0x0412, 0x40, 0x00, 0x00 }, // pipe 2 bpp=0x10, pipe 3 bpp=0x10: Datatypes = 0x2…
290 …{ I2C_DEV_DES, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Po…
291 { I2C_DEV_DES, 2, 0x0006, 0xff, 0x00, 0x64 }, // Enable all links and pipes
297 { I2C_DEV_DES, 2, REG_NULL, 0x00, 0x00, 0x00 },
493 ret = max96712_read_reg(max96712, I2C_DEV_DES, in max96712_check_local_chipid()
553 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
562 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
575 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
584 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
597 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
606 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
619 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
628 max96712_read_reg(max96712, I2C_DEV_DES, in max96712_get_link_lock_state()
655 max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
657 max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
661 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
667 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
674 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
677 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
682 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
685 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
692 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
697 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
702 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
707 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
714 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
719 max96712_write_reg(max96712, I2C_DEV_DES, in max96712_check_link_lock_state()
798 ret = max96712_read_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
819 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
823 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
826 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
834 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
838 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
841 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
849 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
853 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
856 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
864 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
868 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
871 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
884 max96712, I2C_DEV_DES, in max96712_dphy_dpll_predef_set()
905 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_auto_init_deskew()
910 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_auto_init_deskew()
915 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_auto_init_deskew()
920 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_auto_init_deskew()
951 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
955 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
958 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
971 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
975 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
979 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
984 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
990 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
1003 ret |= max96712_write_reg(max96712, I2C_DEV_DES, in max96712_frame_sync_period()
1017 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_mipi_enable()
1021 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_mipi_enable()
1026 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_mipi_enable()
1030 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, in max96712_mipi_enable()
1930 max96712->i2c_addr[I2C_DEV_DES] = client->addr; in max96712_probe()