Lines Matching full:gic
5 * Interrupt architecture for the GIC:
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
113 * The GIC mapping of CPU interfaces does not necessarily match
115 * by the GIC itself.
311 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
320 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
359 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
367 * The GIC encodes the source CPU in GICC_IAR, in gic_handle_irq()
376 handle_domain_irq(gic->domain, irqnr, regs); in gic_handle_irq()
429 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
431 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask()
443 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); in gic_get_cpumask()
454 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument
456 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_cpu_if_up()
461 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) in gic_cpu_if_up()
482 static void gic_dist_init(struct gic_chip_data *gic) in gic_dist_init() argument
486 unsigned int gic_irqs = gic->gic_irqs; in gic_dist_init()
487 void __iomem *base = gic_data_dist_base(gic); in gic_dist_init()
494 cpumask = gic_get_cpumask(gic); in gic_dist_init()
513 static int gic_cpu_init(struct gic_chip_data *gic) in gic_cpu_init() argument
515 void __iomem *dist_base = gic_data_dist_base(gic); in gic_cpu_init()
516 void __iomem *base = gic_data_cpu_base(gic); in gic_cpu_init()
521 * Setting up the CPU map is only relevant for the primary GIC in gic_cpu_init()
525 if (gic == &gic_data[0]) { in gic_cpu_init()
527 * Get what the GIC says our CPU mask is. in gic_cpu_init()
533 cpu_mask = gic_get_cpumask(gic); in gic_cpu_init()
548 gic_cpu_if_up(gic); in gic_cpu_init()
571 * Saves the GIC distributor registers during suspend or idle. Must be called
572 * with interrupts disabled but before powering down the GIC. After calling
573 * this function, no interrupts will be delivered by the GIC, and another
576 void gic_dist_save(struct gic_chip_data *gic) in gic_dist_save() argument
582 if (WARN_ON(!gic)) in gic_dist_save()
585 gic_irqs = gic->gic_irqs; in gic_dist_save()
586 dist_base = gic_data_dist_base(gic); in gic_dist_save()
592 gic->saved_spi_conf[i] = in gic_dist_save()
596 gic->saved_spi_target[i] = in gic_dist_save()
600 gic->saved_spi_enable[i] = in gic_dist_save()
604 gic->saved_spi_active[i] = in gic_dist_save()
609 * Restores the GIC distributor registers during resume or when coming out of
611 * that occurred while the GIC was suspended is still present, it will be
613 * the GIC and need to be handled by the platform-specific wakeup source.
615 void gic_dist_restore(struct gic_chip_data *gic) in gic_dist_restore() argument
621 if (WARN_ON(!gic)) in gic_dist_restore()
624 gic_irqs = gic->gic_irqs; in gic_dist_restore()
625 dist_base = gic_data_dist_base(gic); in gic_dist_restore()
633 writel_relaxed(gic->saved_spi_conf[i], in gic_dist_restore()
641 writel_relaxed(gic->saved_spi_target[i], in gic_dist_restore()
647 writel_relaxed(gic->saved_spi_enable[i], in gic_dist_restore()
654 writel_relaxed(gic->saved_spi_active[i], in gic_dist_restore()
665 void gic_cpu_save(struct gic_chip_data *gic) in gic_cpu_save() argument
672 if (WARN_ON(!gic)) in gic_cpu_save()
675 dist_base = gic_data_dist_base(gic); in gic_cpu_save()
676 cpu_base = gic_data_cpu_base(gic); in gic_cpu_save()
681 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_save()
685 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_save()
689 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_save()
695 void gic_cpu_restore(struct gic_chip_data *gic) in gic_cpu_restore() argument
702 if (WARN_ON(!gic)) in gic_cpu_restore()
705 dist_base = gic_data_dist_base(gic); in gic_cpu_restore()
706 cpu_base = gic_data_cpu_base(gic); in gic_cpu_restore()
711 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_restore()
718 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_restore()
725 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_restore()
734 gic_cpu_if_up(gic); in gic_cpu_restore()
767 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
769 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
771 if (WARN_ON(!gic->saved_ppi_enable)) in gic_pm_init()
774 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
776 if (WARN_ON(!gic->saved_ppi_active)) in gic_pm_init()
779 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, in gic_pm_init()
781 if (WARN_ON(!gic->saved_ppi_conf)) in gic_pm_init()
784 if (gic == &gic_data[0]) in gic_pm_init()
790 free_percpu(gic->saved_ppi_active); in gic_pm_init()
792 free_percpu(gic->saved_ppi_enable); in gic_pm_init()
797 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
893 /* enable non-secure SGI for GIC with security extensions */ in gic_ipi_send_mask()
922 "irqchip/arm/gic:starting", in gic_smp_init()
957 * @cpu: the logical CPU number to get the GIC ID for.
1070 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); in gic_init_physaddr()
1081 struct gic_chip_data *gic = d->host_data; in gic_irq_domain_map() local
1087 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
1093 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
1097 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
1198 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, in gic_init_chip() argument
1202 gic->chip = gic_chip; in gic_init_chip()
1203 gic->chip.name = name; in gic_init_chip()
1204 gic->chip.parent_device = dev; in gic_init_chip()
1207 gic->chip.irq_mask = gic_eoimode1_mask_irq; in gic_init_chip()
1208 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; in gic_init_chip()
1209 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; in gic_init_chip()
1212 if (gic == &gic_data[0]) { in gic_init_chip()
1213 gic->chip.irq_set_affinity = gic_set_affinity; in gic_init_chip()
1214 gic->chip.ipi_send_mask = gic_ipi_send_mask; in gic_init_chip()
1218 static int gic_init_bases(struct gic_chip_data *gic, in gic_init_bases() argument
1223 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1224 /* Frankein-GIC without banked registers... */ in gic_init_bases()
1227 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1228 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1229 if (WARN_ON(!gic->dist_base.percpu_base || in gic_init_bases()
1230 !gic->cpu_base.percpu_base)) { in gic_init_bases()
1238 unsigned long offset = gic->percpu_offset * core_id; in gic_init_bases()
1239 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = in gic_init_bases()
1240 gic->raw_dist_base + offset; in gic_init_bases()
1241 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = in gic_init_bases()
1242 gic->raw_cpu_base + offset; in gic_init_bases()
1247 /* Normal, sane GIC... */ in gic_init_bases()
1248 WARN(gic->percpu_offset, in gic_init_bases()
1250 gic->percpu_offset); in gic_init_bases()
1251 gic->dist_base.common_base = gic->raw_dist_base; in gic_init_bases()
1252 gic->cpu_base.common_base = gic->raw_cpu_base; in gic_init_bases()
1257 * The GIC only supports up to 1020 interrupt sources. in gic_init_bases()
1259 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; in gic_init_bases()
1263 gic->gic_irqs = gic_irqs; in gic_init_bases()
1266 gic->domain = irq_domain_create_linear(handle, gic_irqs, in gic_init_bases()
1268 gic); in gic_init_bases()
1272 * No secondary GIC support whatsoever. in gic_init_bases()
1285 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, in gic_init_bases()
1286 16, &gic_irq_domain_ops, gic); in gic_init_bases()
1289 if (WARN_ON(!gic->domain)) { in gic_init_bases()
1294 gic_dist_init(gic); in gic_init_bases()
1295 ret = gic_cpu_init(gic); in gic_init_bases()
1299 ret = gic_pm_init(gic); in gic_init_bases()
1306 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1307 free_percpu(gic->dist_base.percpu_base); in gic_init_bases()
1308 free_percpu(gic->cpu_base.percpu_base); in gic_init_bases()
1314 static int __init __gic_init_bases(struct gic_chip_data *gic, in __gic_init_bases() argument
1320 if (WARN_ON(!gic || gic->domain)) in __gic_init_bases()
1323 if (gic == &gic_data[0]) { in __gic_init_bases()
1327 * This is only necessary for the primary GIC. in __gic_init_bases()
1334 pr_info("GIC: Using split EOI/Deactivate mode\n"); in __gic_init_bases()
1337 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { in __gic_init_bases()
1339 gic_init_chip(gic, NULL, name, true); in __gic_init_bases()
1341 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); in __gic_init_bases()
1342 gic_init_chip(gic, NULL, name, false); in __gic_init_bases()
1345 ret = gic_init_bases(gic, handle); in __gic_init_bases()
1348 else if (gic == &gic_data[0]) in __gic_init_bases()
1356 struct gic_chip_data *gic; in gic_init() local
1364 gic = &gic_data[0]; in gic_init()
1365 gic->raw_dist_base = dist_base; in gic_init()
1366 gic->raw_cpu_base = cpu_base; in gic_init()
1368 __gic_init_bases(gic, NULL); in gic_init()
1371 static void gic_teardown(struct gic_chip_data *gic) in gic_teardown() argument
1373 if (WARN_ON(!gic)) in gic_teardown()
1376 if (gic->raw_dist_base) in gic_teardown()
1377 iounmap(gic->raw_dist_base); in gic_teardown()
1378 if (gic->raw_cpu_base) in gic_teardown()
1379 iounmap(gic->raw_cpu_base); in gic_teardown()
1410 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1423 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1440 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1463 pr_warn("GIC: Adjusting CPU interface base to %pa\n", in gic_check_eoimode()
1494 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) in gic_of_setup() argument
1496 if (!gic || !node) in gic_of_setup()
1499 gic->raw_dist_base = of_iomap(node, 0); in gic_of_setup()
1500 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) in gic_of_setup()
1503 gic->raw_cpu_base = of_iomap(node, 1); in gic_of_setup()
1504 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) in gic_of_setup()
1507 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) in gic_of_setup()
1508 gic->percpu_offset = 0; in gic_of_setup()
1510 gic_enable_of_quirks(node, gic_quirks, gic); in gic_of_setup()
1515 gic_teardown(gic); in gic_of_setup()
1520 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1524 if (!dev || !dev->of_node || !gic || !irq) in gic_of_init_child()
1527 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); in gic_of_init_child()
1528 if (!*gic) in gic_of_init_child()
1531 gic_init_chip(*gic, dev, dev->of_node->name, false); in gic_of_init_child()
1533 ret = gic_of_setup(*gic, dev->of_node); in gic_of_init_child()
1537 ret = gic_init_bases(*gic, &dev->of_node->fwnode); in gic_of_init_child()
1539 gic_teardown(*gic); in gic_of_init_child()
1543 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); in gic_of_init_child()
1575 struct gic_chip_data *gic; in gic_of_init() local
1584 gic = &gic_data[gic_cnt]; in gic_of_init()
1586 ret = gic_of_setup(gic, node); in gic_of_init()
1594 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) in gic_of_init()
1597 ret = __gic_init_bases(gic, &node->fwnode); in gic_of_init()
1599 gic_teardown(gic); in gic_of_init()
1619 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1620 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1621 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1622 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1623 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1624 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1629 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1744 struct gic_chip_data *gic = &gic_data[0]; in gic_v2_acpi_init() local
1755 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); in gic_v2_acpi_init()
1756 if (!gic->raw_cpu_base) { in gic_v2_acpi_init()
1762 gic->raw_dist_base = ioremap(dist->base_address, in gic_v2_acpi_init()
1764 if (!gic->raw_dist_base) { in gic_v2_acpi_init()
1766 gic_teardown(gic); in gic_v2_acpi_init()
1779 * Initialize GIC instance zero (no multi-GIC support). in gic_v2_acpi_init()
1784 gic_teardown(gic); in gic_v2_acpi_init()
1788 ret = __gic_init_bases(gic, domain_handle); in gic_v2_acpi_init()
1790 pr_err("Failed to initialise GIC\n"); in gic_v2_acpi_init()
1792 gic_teardown(gic); in gic_v2_acpi_init()