Lines Matching +full:gic +full:- +full:its
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
14 #include <linux/dma-iommu.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
40 #include "irq-gic-common.h"
63 * Collection structure - just an ID, and a redistributor address to
73 * The ITS_BASER structure - contains memory information, cached
74 * value of BASER register configuration and ITS page size.
86 * The ITS structure - contains most of the infrastructure, with the
87 * top-level MSI domain, the command queue, the collections, and the
120 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS)) argument
121 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP)) argument
122 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1) argument
130 if (gic_rdists->has_rvpeid && \
131 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
132 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
154 * The ITS view of a device - belongs to an ITS, owns an interrupt
155 * translation table, and a list of interrupts. If it some of its
161 struct its_node *its; member
195 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
196 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
197 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
204 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) in require_its_list_vmovp() argument
206 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); in require_its_list_vmovp()
211 struct its_node *its; in get_its_list() local
214 list_for_each_entry(its, &its_nodes, entry) { in get_its_list()
215 if (!is_v4(its)) in get_its_list()
218 if (require_its_list_vmovp(vm, its)) in get_its_list()
219 __set_bit(its->list_nr, &its_list); in get_its_list()
228 return d->hwirq - its_dev->event_map.lpi_base; in its_get_event_id()
234 struct its_node *its = its_dev->its; in dev_event_to_col() local
236 return its->collections + its_dev->event_map.col_map[event]; in dev_event_to_col()
242 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) in dev_event_to_vlpi_map()
245 return &its_dev->event_map.vlpi_maps[event]; in dev_event_to_vlpi_map()
262 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); in vpe_to_cpuid_lock()
263 return vpe->col_idx; in vpe_to_cpuid_lock()
268 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in vpe_to_cpuid_unlock()
277 cpu = vpe_to_cpuid_lock(map->vpe, flags); in irq_to_cpuid_lock()
281 cpu = its_dev->event_map.col_map[its_get_event_id(d)]; in irq_to_cpuid_lock()
294 vpe_to_cpuid_unlock(map->vpe, flags); in irq_to_cpuid_unlock()
299 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) in valid_col()
305 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) in valid_vpe() argument
307 if (valid_col(its->collections + vpe->col_idx)) in valid_vpe()
314 * ITS command descriptors - parameters to be encoded in a command
413 * The ITS command block, which is what the ITS actually parses.
442 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); in its_encode_cmd()
447 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); in its_encode_devid()
452 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); in its_encode_event_id()
457 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); in its_encode_phys_id()
462 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); in its_encode_size()
467 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); in its_encode_itt()
472 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); in its_encode_valid()
477 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); in its_encode_target()
482 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); in its_encode_collection()
487 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); in its_encode_vpeid()
492 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); in its_encode_virt_id()
497 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); in its_encode_db_phys_id()
502 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); in its_encode_db_valid()
507 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); in its_encode_seq_num()
512 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); in its_encode_its_list()
517 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); in its_encode_vpt_addr()
522 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); in its_encode_vpt_size()
527 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); in its_encode_vconf_addr()
532 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); in its_encode_alloc()
537 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); in its_encode_ptz()
543 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); in its_encode_vmapp_default_db()
549 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0); in its_encode_vmovp_default_db()
554 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); in its_encode_db()
559 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); in its_encode_sgi_intid()
564 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); in its_encode_sgi_priority()
569 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); in its_encode_sgi_group()
574 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); in its_encode_sgi_clear()
579 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); in its_encode_sgi_enable()
585 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); in its_fixup_cmd()
586 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); in its_fixup_cmd()
587 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); in its_fixup_cmd()
588 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); in its_fixup_cmd()
591 static struct its_collection *its_build_mapd_cmd(struct its_node *its, in its_build_mapd_cmd() argument
596 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); in its_build_mapd_cmd()
598 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); in its_build_mapd_cmd()
602 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); in its_build_mapd_cmd()
603 its_encode_size(cmd, size - 1); in its_build_mapd_cmd()
605 its_encode_valid(cmd, desc->its_mapd_cmd.valid); in its_build_mapd_cmd()
612 static struct its_collection *its_build_mapc_cmd(struct its_node *its, in its_build_mapc_cmd() argument
617 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); in its_build_mapc_cmd()
618 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); in its_build_mapc_cmd()
619 its_encode_valid(cmd, desc->its_mapc_cmd.valid); in its_build_mapc_cmd()
623 return desc->its_mapc_cmd.col; in its_build_mapc_cmd()
626 static struct its_collection *its_build_mapti_cmd(struct its_node *its, in its_build_mapti_cmd() argument
632 col = dev_event_to_col(desc->its_mapti_cmd.dev, in its_build_mapti_cmd()
633 desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
636 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); in its_build_mapti_cmd()
637 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
638 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); in its_build_mapti_cmd()
639 its_encode_collection(cmd, col->col_id); in its_build_mapti_cmd()
646 static struct its_collection *its_build_movi_cmd(struct its_node *its, in its_build_movi_cmd() argument
652 col = dev_event_to_col(desc->its_movi_cmd.dev, in its_build_movi_cmd()
653 desc->its_movi_cmd.event_id); in its_build_movi_cmd()
656 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); in its_build_movi_cmd()
657 its_encode_event_id(cmd, desc->its_movi_cmd.event_id); in its_build_movi_cmd()
658 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); in its_build_movi_cmd()
665 static struct its_collection *its_build_discard_cmd(struct its_node *its, in its_build_discard_cmd() argument
671 col = dev_event_to_col(desc->its_discard_cmd.dev, in its_build_discard_cmd()
672 desc->its_discard_cmd.event_id); in its_build_discard_cmd()
675 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); in its_build_discard_cmd()
676 its_encode_event_id(cmd, desc->its_discard_cmd.event_id); in its_build_discard_cmd()
683 static struct its_collection *its_build_inv_cmd(struct its_node *its, in its_build_inv_cmd() argument
689 col = dev_event_to_col(desc->its_inv_cmd.dev, in its_build_inv_cmd()
690 desc->its_inv_cmd.event_id); in its_build_inv_cmd()
693 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_inv_cmd()
694 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_inv_cmd()
701 static struct its_collection *its_build_int_cmd(struct its_node *its, in its_build_int_cmd() argument
707 col = dev_event_to_col(desc->its_int_cmd.dev, in its_build_int_cmd()
708 desc->its_int_cmd.event_id); in its_build_int_cmd()
711 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_int_cmd()
712 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_int_cmd()
719 static struct its_collection *its_build_clear_cmd(struct its_node *its, in its_build_clear_cmd() argument
725 col = dev_event_to_col(desc->its_clear_cmd.dev, in its_build_clear_cmd()
726 desc->its_clear_cmd.event_id); in its_build_clear_cmd()
729 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_clear_cmd()
730 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_clear_cmd()
737 static struct its_collection *its_build_invall_cmd(struct its_node *its, in its_build_invall_cmd() argument
742 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); in its_build_invall_cmd()
746 return desc->its_invall_cmd.col; in its_build_invall_cmd()
749 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, in its_build_vinvall_cmd() argument
754 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); in its_build_vinvall_cmd()
758 return valid_vpe(its, desc->its_vinvall_cmd.vpe); in its_build_vinvall_cmd()
761 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, in its_build_vmapp_cmd() argument
770 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); in its_build_vmapp_cmd()
771 its_encode_valid(cmd, desc->its_vmapp_cmd.valid); in its_build_vmapp_cmd()
773 if (!desc->its_vmapp_cmd.valid) { in its_build_vmapp_cmd()
774 if (is_v4_1(its)) { in its_build_vmapp_cmd()
775 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
782 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); in its_build_vmapp_cmd()
783 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmapp_cmd()
787 its_encode_vpt_size(cmd, LPI_NRBITS - 1); in its_build_vmapp_cmd()
789 if (!is_v4_1(its)) in its_build_vmapp_cmd()
792 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); in its_build_vmapp_cmd()
794 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
801 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); in its_build_vmapp_cmd()
806 return valid_vpe(its, desc->its_vmapp_cmd.vpe); in its_build_vmapp_cmd()
809 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, in its_build_vmapti_cmd() argument
815 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled) in its_build_vmapti_cmd()
816 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; in its_build_vmapti_cmd()
821 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); in its_build_vmapti_cmd()
822 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); in its_build_vmapti_cmd()
823 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); in its_build_vmapti_cmd()
825 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); in its_build_vmapti_cmd()
829 return valid_vpe(its, desc->its_vmapti_cmd.vpe); in its_build_vmapti_cmd()
832 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, in its_build_vmovi_cmd() argument
838 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled) in its_build_vmovi_cmd()
839 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; in its_build_vmovi_cmd()
844 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); in its_build_vmovi_cmd()
845 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); in its_build_vmovi_cmd()
846 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); in its_build_vmovi_cmd()
852 return valid_vpe(its, desc->its_vmovi_cmd.vpe); in its_build_vmovi_cmd()
855 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, in its_build_vmovp_cmd() argument
861 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmovp_cmd()
863 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); in its_build_vmovp_cmd()
864 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); in its_build_vmovp_cmd()
865 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); in its_build_vmovp_cmd()
868 if (is_v4_1(its)) { in its_build_vmovp_cmd()
870 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi); in its_build_vmovp_cmd()
875 return valid_vpe(its, desc->its_vmovp_cmd.vpe); in its_build_vmovp_cmd()
878 static struct its_vpe *its_build_vinv_cmd(struct its_node *its, in its_build_vinv_cmd() argument
884 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, in its_build_vinv_cmd()
885 desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
888 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_vinv_cmd()
889 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
893 return valid_vpe(its, map->vpe); in its_build_vinv_cmd()
896 static struct its_vpe *its_build_vint_cmd(struct its_node *its, in its_build_vint_cmd() argument
902 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, in its_build_vint_cmd()
903 desc->its_int_cmd.event_id); in its_build_vint_cmd()
906 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_vint_cmd()
907 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_vint_cmd()
911 return valid_vpe(its, map->vpe); in its_build_vint_cmd()
914 static struct its_vpe *its_build_vclear_cmd(struct its_node *its, in its_build_vclear_cmd() argument
920 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, in its_build_vclear_cmd()
921 desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
924 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_vclear_cmd()
925 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
929 return valid_vpe(its, map->vpe); in its_build_vclear_cmd()
932 static struct its_vpe *its_build_invdb_cmd(struct its_node *its, in its_build_invdb_cmd() argument
936 if (WARN_ON(!is_v4_1(its))) in its_build_invdb_cmd()
940 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id); in its_build_invdb_cmd()
944 return valid_vpe(its, desc->its_invdb_cmd.vpe); in its_build_invdb_cmd()
947 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its, in its_build_vsgi_cmd() argument
951 if (WARN_ON(!is_v4_1(its))) in its_build_vsgi_cmd()
955 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); in its_build_vsgi_cmd()
956 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); in its_build_vsgi_cmd()
957 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); in its_build_vsgi_cmd()
958 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); in its_build_vsgi_cmd()
959 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); in its_build_vsgi_cmd()
960 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); in its_build_vsgi_cmd()
964 return valid_vpe(its, desc->its_vsgi_cmd.vpe); in its_build_vsgi_cmd()
967 static u64 its_cmd_ptr_to_offset(struct its_node *its, in its_cmd_ptr_to_offset() argument
970 return (ptr - its->cmd_base) * sizeof(*ptr); in its_cmd_ptr_to_offset()
973 static int its_queue_full(struct its_node *its) in its_queue_full() argument
978 widx = its->cmd_write - its->cmd_base; in its_queue_full()
979 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); in its_queue_full()
981 /* This is incredibly unlikely to happen, unless the ITS locks up. */ in its_queue_full()
988 static struct its_cmd_block *its_allocate_entry(struct its_node *its) in its_allocate_entry() argument
993 while (its_queue_full(its)) { in its_allocate_entry()
994 count--; in its_allocate_entry()
996 pr_err_ratelimited("ITS queue not draining\n"); in its_allocate_entry()
1003 cmd = its->cmd_write++; in its_allocate_entry()
1006 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) in its_allocate_entry()
1007 its->cmd_write = its->cmd_base; in its_allocate_entry()
1010 cmd->raw_cmd[0] = 0; in its_allocate_entry()
1011 cmd->raw_cmd[1] = 0; in its_allocate_entry()
1012 cmd->raw_cmd[2] = 0; in its_allocate_entry()
1013 cmd->raw_cmd[3] = 0; in its_allocate_entry()
1018 static struct its_cmd_block *its_post_commands(struct its_node *its) in its_post_commands() argument
1020 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); in its_post_commands()
1022 writel_relaxed(wr, its->base + GITS_CWRITER); in its_post_commands()
1024 return its->cmd_write; in its_post_commands()
1027 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) in its_flush_cmd() argument
1031 * the ITS. in its_flush_cmd()
1033 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) in its_flush_cmd()
1039 static int its_wait_for_range_completion(struct its_node *its, in its_wait_for_range_completion() argument
1047 to_idx = its_cmd_ptr_to_offset(its, to); in its_wait_for_range_completion()
1056 rd_idx = readl_relaxed(its->base + GITS_CREADR); in its_wait_for_range_completion()
1060 * potential wrap-around into account. in its_wait_for_range_completion()
1062 delta = rd_idx - prev_idx; in its_wait_for_range_completion()
1070 count--; in its_wait_for_range_completion()
1072 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n", in its_wait_for_range_completion()
1074 return -1; in its_wait_for_range_completion()
1086 void name(struct its_node *its, \
1095 raw_spin_lock_irqsave(&its->lock, flags); \
1097 cmd = its_allocate_entry(its); \
1099 raw_spin_unlock_irqrestore(&its->lock, flags); \
1102 sync_obj = builder(its, cmd, desc); \
1103 its_flush_cmd(its, cmd); \
1106 sync_cmd = its_allocate_entry(its); \
1110 buildfn(its, sync_cmd, sync_obj); \
1111 its_flush_cmd(its, sync_cmd); \
1115 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1116 next_cmd = its_post_commands(its); \
1117 raw_spin_unlock_irqrestore(&its->lock, flags); \
1119 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1120 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1123 static void its_build_sync_cmd(struct its_node *its, in its_build_sync_cmd() argument
1128 its_encode_target(sync_cmd, sync_col->target_address); in its_build_sync_cmd()
1136 static void its_build_vsync_cmd(struct its_node *its, in BUILD_SINGLE_CMD_FUNC()
1141 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); in BUILD_SINGLE_CMD_FUNC()
1156 its_send_single_command(dev->its, its_build_int_cmd, &desc); in BUILD_SINGLE_CMD_FUNC()
1166 its_send_single_command(dev->its, its_build_clear_cmd, &desc); in its_send_clear()
1176 its_send_single_command(dev->its, its_build_inv_cmd, &desc); in its_send_inv()
1186 its_send_single_command(dev->its, its_build_mapd_cmd, &desc); in its_send_mapd()
1189 static void its_send_mapc(struct its_node *its, struct its_collection *col, in its_send_mapc() argument
1197 its_send_single_command(its, its_build_mapc_cmd, &desc); in its_send_mapc()
1208 its_send_single_command(dev->its, its_build_mapti_cmd, &desc); in its_send_mapti()
1220 its_send_single_command(dev->its, its_build_movi_cmd, &desc); in its_send_movi()
1230 its_send_single_command(dev->its, its_build_discard_cmd, &desc); in its_send_discard()
1233 static void its_send_invall(struct its_node *its, struct its_collection *col) in its_send_invall() argument
1239 its_send_single_command(its, its_build_invall_cmd, &desc); in its_send_invall()
1247 desc.its_vmapti_cmd.vpe = map->vpe; in its_send_vmapti()
1249 desc.its_vmapti_cmd.virt_id = map->vintid; in its_send_vmapti()
1251 desc.its_vmapti_cmd.db_enabled = map->db_enabled; in its_send_vmapti()
1253 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); in its_send_vmapti()
1261 desc.its_vmovi_cmd.vpe = map->vpe; in its_send_vmovi()
1264 desc.its_vmovi_cmd.db_enabled = map->db_enabled; in its_send_vmovi()
1266 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); in its_send_vmovi()
1269 static void its_send_vmapp(struct its_node *its, in its_send_vmapp() argument
1276 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; in its_send_vmapp()
1278 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); in its_send_vmapp()
1284 struct its_node *its; in its_send_vmovp() local
1286 int col_id = vpe->col_idx; in its_send_vmovp()
1291 its = list_first_entry(&its_nodes, struct its_node, entry); in its_send_vmovp()
1292 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1293 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); in its_send_vmovp()
1303 * Wall <-- Head. in its_send_vmovp()
1308 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); in its_send_vmovp()
1311 list_for_each_entry(its, &its_nodes, entry) { in its_send_vmovp()
1312 if (!is_v4(its)) in its_send_vmovp()
1315 if (!require_its_list_vmovp(vpe->its_vm, its)) in its_send_vmovp()
1318 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1319 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); in its_send_vmovp()
1325 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) in its_send_vinvall() argument
1330 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); in its_send_vinvall()
1344 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); in its_send_vinv()
1358 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); in its_send_vint()
1372 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); in its_send_vclear()
1375 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe) in its_send_invdb() argument
1380 its_send_single_vcommand(its, its_build_invdb_cmd, &desc); in its_send_invdb()
1384 * irqchip functions - assumes MSI, mostly.
1394 va = page_address(map->vm->vprop_page); in lpi_write_config()
1395 hwirq = map->vintid; in lpi_write_config()
1398 map->properties &= ~clr; in lpi_write_config()
1399 map->properties |= set | LPI_PROP_GROUP1; in lpi_write_config()
1401 va = gic_rdists->prop_table_va; in lpi_write_config()
1402 hwirq = d->hwirq; in lpi_write_config()
1405 cfg = va + hwirq - 8192; in lpi_write_config()
1414 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) in lpi_write_config()
1437 WARN_ON(!is_v4_1(its_dev->its)); in direct_lpi_inv()
1440 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id); in direct_lpi_inv()
1441 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid); in direct_lpi_inv()
1443 val = d->hwirq; in direct_lpi_inv()
1448 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in direct_lpi_inv()
1449 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in direct_lpi_inv()
1453 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in direct_lpi_inv()
1462 if (gic_rdists->has_direct_lpi && in lpi_update_config()
1463 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d))) in lpi_update_config()
1478 * GICv4.1 does away with the per-LPI nonsense, nothing to do in its_vlpi_set_doorbell()
1481 if (is_v4_1(its_dev->its)) in its_vlpi_set_doorbell()
1486 if (map->db_enabled == enable) in its_vlpi_set_doorbell()
1489 map->db_enabled = enable; in its_vlpi_set_doorbell()
1494 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI in its_vlpi_set_doorbell()
1523 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_read_lpi_count()
1525 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_read_lpi_count()
1531 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_inc_lpi_count()
1533 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_inc_lpi_count()
1539 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_dec_lpi_count()
1541 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_dec_lpi_count()
1573 return -ENOMEM; in its_select_cpu()
1575 node = its_dev->its->numa_node; in its_select_cpu()
1594 * ITS placed next to two NUMA nodes. in its_select_cpu()
1604 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)) in its_select_cpu()
1622 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) && in its_select_cpu()
1631 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); in its_select_cpu()
1645 return -EINVAL; in its_set_affinity()
1647 prev_cpu = its_dev->event_map.col_map[id]; in its_set_affinity()
1660 target_col = &its_dev->its->collections[cpu]; in its_set_affinity()
1662 its_dev->event_map.col_map[id] = cpu; in its_set_affinity()
1672 return -EINVAL; in its_set_affinity()
1677 struct its_node *its = its_dev->its; in its_irq_get_msi_base() local
1679 return its->phys_base + GITS_TRANSLATER; in its_irq_get_msi_base()
1685 struct its_node *its; in its_irq_compose_msi_msg() local
1688 its = its_dev->its; in its_irq_compose_msi_msg()
1689 addr = its->get_msi_base(its_dev); in its_irq_compose_msi_msg()
1691 msg->address_lo = lower_32_bits(addr); in its_irq_compose_msi_msg()
1692 msg->address_hi = upper_32_bits(addr); in its_irq_compose_msi_msg()
1693 msg->data = its_get_event_id(d); in its_irq_compose_msi_msg()
1706 return -EINVAL; in its_irq_set_irqchip_state()
1742 if (!its_list_map || gic_rdists->has_rvpeid) in gic_requires_eager_mapping()
1748 static void its_map_vm(struct its_node *its, struct its_vm *vm) in its_map_vm() argument
1761 vm->vlpi_count[its->list_nr]++; in its_map_vm()
1763 if (vm->vlpi_count[its->list_nr] == 1) { in its_map_vm()
1766 for (i = 0; i < vm->nr_vpes; i++) { in its_map_vm()
1767 struct its_vpe *vpe = vm->vpes[i]; in its_map_vm()
1768 struct irq_data *d = irq_get_irq_data(vpe->irq); in its_map_vm()
1771 vpe->col_idx = cpumask_first(cpu_online_mask); in its_map_vm()
1772 its_send_vmapp(its, vpe, true); in its_map_vm()
1773 its_send_vinvall(its, vpe); in its_map_vm()
1774 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_map_vm()
1781 static void its_unmap_vm(struct its_node *its, struct its_vm *vm) in its_unmap_vm() argument
1785 /* Not using the ITS list? Everything is always mapped. */ in its_unmap_vm()
1791 if (!--vm->vlpi_count[its->list_nr]) { in its_unmap_vm()
1794 for (i = 0; i < vm->nr_vpes; i++) in its_unmap_vm()
1795 its_send_vmapp(its, vm->vpes[i], false); in its_unmap_vm()
1807 if (!info->map) in its_vlpi_map()
1808 return -EINVAL; in its_vlpi_map()
1810 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_map()
1812 if (!its_dev->event_map.vm) { in its_vlpi_map()
1815 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), in its_vlpi_map()
1818 ret = -ENOMEM; in its_vlpi_map()
1822 its_dev->event_map.vm = info->map->vm; in its_vlpi_map()
1823 its_dev->event_map.vlpi_maps = maps; in its_vlpi_map()
1824 } else if (its_dev->event_map.vm != info->map->vm) { in its_vlpi_map()
1825 ret = -EINVAL; in its_vlpi_map()
1830 its_dev->event_map.vlpi_maps[event] = *info->map; in its_vlpi_map()
1836 /* Ensure all the VPEs are mapped on this ITS */ in its_vlpi_map()
1837 its_map_vm(its_dev->its, info->map->vm); in its_vlpi_map()
1846 lpi_write_config(d, 0xff, info->map->properties); in its_vlpi_map()
1855 its_dev->event_map.nr_vlpis++; in its_vlpi_map()
1859 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_map()
1869 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_get()
1873 if (!its_dev->event_map.vm || !map) { in its_vlpi_get()
1874 ret = -EINVAL; in its_vlpi_get()
1879 *info->map = *map; in its_vlpi_get()
1882 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_get()
1892 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_unmap()
1894 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { in its_vlpi_unmap()
1895 ret = -EINVAL; in its_vlpi_unmap()
1904 its_send_mapti(its_dev, d->hwirq, event); in its_vlpi_unmap()
1909 /* Potentially unmap the VM from this ITS */ in its_vlpi_unmap()
1910 its_unmap_vm(its_dev->its, its_dev->event_map.vm); in its_vlpi_unmap()
1916 if (!--its_dev->event_map.nr_vlpis) { in its_vlpi_unmap()
1917 its_dev->event_map.vm = NULL; in its_vlpi_unmap()
1918 kfree(its_dev->event_map.vlpi_maps); in its_vlpi_unmap()
1922 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_unmap()
1930 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) in its_vlpi_prop_update()
1931 return -EINVAL; in its_vlpi_prop_update()
1933 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) in its_vlpi_prop_update()
1934 lpi_update_config(d, 0xff, info->config); in its_vlpi_prop_update()
1936 lpi_write_config(d, 0xff, info->config); in its_vlpi_prop_update()
1937 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); in its_vlpi_prop_update()
1947 /* Need a v4 ITS */ in its_irq_set_vcpu_affinity()
1948 if (!is_v4(its_dev->its)) in its_irq_set_vcpu_affinity()
1949 return -EINVAL; in its_irq_set_vcpu_affinity()
1955 switch (info->cmd_type) { in its_irq_set_vcpu_affinity()
1967 return -EINVAL; in its_irq_set_vcpu_affinity()
1972 .name = "ITS",
2016 range->base_id = base; in mk_lpi_range()
2017 range->span = span; in mk_lpi_range()
2026 int err = -ENOSPC; in alloc_lpi_range()
2031 if (range->span >= nr_lpis) { in alloc_lpi_range()
2032 *base = range->base_id; in alloc_lpi_range()
2033 range->base_id += nr_lpis; in alloc_lpi_range()
2034 range->span -= nr_lpis; in alloc_lpi_range()
2036 if (range->span == 0) { in alloc_lpi_range()
2037 list_del(&range->entry); in alloc_lpi_range()
2048 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); in alloc_lpi_range()
2054 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) in merge_lpi_ranges()
2056 if (a->base_id + a->span != b->base_id) in merge_lpi_ranges()
2058 b->base_id = a->base_id; in merge_lpi_ranges()
2059 b->span += a->span; in merge_lpi_ranges()
2060 list_del(&a->entry); in merge_lpi_ranges()
2070 return -ENOMEM; in free_lpi_range()
2075 if (old->base_id < base) in free_lpi_range()
2079 * old is the last element with ->base_id smaller than base, in free_lpi_range()
2081 * ->base_id smaller than base, &old->entry ends up pointing in free_lpi_range()
2085 list_add(&new->entry, &old->entry); in free_lpi_range()
2099 u32 lpis = (1UL << id_bits) - 8192; in its_lpi_init()
2103 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); in its_lpi_init()
2107 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", in its_lpi_init()
2116 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); in its_lpi_init()
2134 err = -ENOSPC; in its_lpi_alloc()
2160 /* Priority 0xa0, Group-1, disabled */ in gic_reset_prop_table()
2163 /* Make sure the GIC will observe the written configuration */ in gic_reset_prop_table()
2201 addr_end = addr + size - 1; in gic_check_reserved_range()
2225 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { in its_setup_lpi_prop_table()
2231 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); in its_setup_lpi_prop_table()
2232 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2235 gic_reset_prop_table(gic_rdists->prop_table_va); in its_setup_lpi_prop_table()
2240 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), in its_setup_lpi_prop_table()
2245 return -ENOMEM; in its_setup_lpi_prop_table()
2248 gic_rdists->prop_table_pa = page_to_phys(page); in its_setup_lpi_prop_table()
2249 gic_rdists->prop_table_va = page_address(page); in its_setup_lpi_prop_table()
2250 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2255 &gic_rdists->prop_table_pa); in its_setup_lpi_prop_table()
2270 static u64 its_read_baser(struct its_node *its, struct its_baser *baser) in its_read_baser() argument
2272 u32 idx = baser - its->tables; in its_read_baser()
2274 return gits_read_baser(its->base + GITS_BASER + (idx << 3)); in its_read_baser()
2277 static void its_write_baser(struct its_node *its, struct its_baser *baser, in its_write_baser() argument
2280 u32 idx = baser - its->tables; in its_write_baser()
2282 gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); in its_write_baser()
2283 baser->val = its_read_baser(its, baser); in its_write_baser()
2286 static int its_setup_baser(struct its_node *its, struct its_baser *baser, in its_setup_baser() argument
2289 u64 val = its_read_baser(its, baser); in its_setup_baser()
2298 psz = baser->psz; in its_setup_baser()
2301 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", in its_setup_baser()
2302 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2311 page = alloc_pages_node(its->numa_node, gfp_flags, order); in its_setup_baser()
2313 return -ENOMEM; in its_setup_baser()
2323 pr_err("ITS: no 52bit PA support when psz=%d\n", psz); in its_setup_baser()
2325 return -ENXIO; in its_setup_baser()
2335 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | in its_setup_baser()
2336 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | in its_setup_baser()
2355 its_write_baser(its, baser, val); in its_setup_baser()
2356 tmp = baser->val; in its_setup_baser()
2374 * non-cacheable as well. in its_setup_baser()
2385 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", in its_setup_baser()
2386 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2389 return -ENXIO; in its_setup_baser()
2392 baser->order = order; in its_setup_baser()
2393 baser->base = base; in its_setup_baser()
2394 baser->psz = psz; in its_setup_baser()
2397 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", in its_setup_baser()
2398 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), in its_setup_baser()
2407 static bool its_parse_indirect_baser(struct its_node *its, in its_parse_indirect_baser() argument
2411 u64 tmp = its_read_baser(its, baser); in its_parse_indirect_baser()
2416 u32 psz = baser->psz; in its_parse_indirect_baser()
2422 * Find out whether hw supports a single or two-level table by in its_parse_indirect_baser()
2425 its_write_baser(its, baser, val | GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2426 indirect = !!(baser->val & GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2430 * The size of the lvl2 table is equal to ITS page size in its_parse_indirect_baser()
2433 * which is reported by ITS hardware times lvl1 table in its_parse_indirect_baser()
2436 ids -= ilog2(psz / (int)esz); in its_parse_indirect_baser()
2443 * range of device IDs that the ITS can grok... The ID in its_parse_indirect_baser()
2445 * massive waste of memory if two-level device table in its_parse_indirect_baser()
2450 new_order = MAX_ORDER - 1; in its_parse_indirect_baser()
2452 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", in its_parse_indirect_baser()
2453 &its->phys_base, its_base_type_string[type], in its_parse_indirect_baser()
2454 device_ids(its), ids); in its_parse_indirect_baser()
2472 static u32 compute_its_aff(struct its_node *its) in compute_its_aff() argument
2478 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute in compute_its_aff()
2482 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); in compute_its_aff()
2484 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); in compute_its_aff()
2490 struct its_node *its; in find_sibling_its() local
2493 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) in find_sibling_its()
2498 list_for_each_entry(its, &its_nodes, entry) { in find_sibling_its()
2501 if (!is_v4_1(its) || its == cur_its) in find_sibling_its()
2504 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in find_sibling_its()
2507 if (aff != compute_its_aff(its)) in find_sibling_its()
2511 baser = its->tables[2].val; in find_sibling_its()
2515 return its; in find_sibling_its()
2521 static void its_free_tables(struct its_node *its) in its_free_tables() argument
2526 if (its->tables[i].base) { in its_free_tables()
2527 free_pages((unsigned long)its->tables[i].base, in its_free_tables()
2528 its->tables[i].order); in its_free_tables()
2529 its->tables[i].base = NULL; in its_free_tables()
2534 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser) in its_probe_baser_psz() argument
2541 val = its_read_baser(its, baser); in its_probe_baser_psz()
2560 its_write_baser(its, baser, val); in its_probe_baser_psz()
2562 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) in its_probe_baser_psz()
2574 return -1; in its_probe_baser_psz()
2578 baser->psz = psz; in its_probe_baser_psz()
2582 static int its_alloc_tables(struct its_node *its) in its_alloc_tables() argument
2588 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) in its_alloc_tables()
2593 struct its_baser *baser = its->tables + i; in its_alloc_tables()
2594 u64 val = its_read_baser(its, baser); in its_alloc_tables()
2602 if (its_probe_baser_psz(its, baser)) { in its_alloc_tables()
2603 its_free_tables(its); in its_alloc_tables()
2604 return -ENXIO; in its_alloc_tables()
2607 order = get_order(baser->psz); in its_alloc_tables()
2611 indirect = its_parse_indirect_baser(its, baser, &order, in its_alloc_tables()
2612 device_ids(its)); in its_alloc_tables()
2616 if (is_v4_1(its)) { in its_alloc_tables()
2620 if ((sibling = find_sibling_its(its))) { in its_alloc_tables()
2621 *baser = sibling->tables[2]; in its_alloc_tables()
2622 its_write_baser(its, baser, baser->val); in its_alloc_tables()
2627 indirect = its_parse_indirect_baser(its, baser, &order, in its_alloc_tables()
2632 err = its_setup_baser(its, baser, cache, shr, order, indirect); in its_alloc_tables()
2634 its_free_tables(its); in its_alloc_tables()
2639 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; in its_alloc_tables()
2640 shr = baser->val & GITS_BASER_SHAREABILITY_MASK; in its_alloc_tables()
2648 struct its_node *its; in inherit_vpe_l1_table_from_its() local
2655 list_for_each_entry(its, &its_nodes, entry) { in inherit_vpe_l1_table_from_its()
2658 if (!is_v4_1(its)) in inherit_vpe_l1_table_from_its()
2661 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in inherit_vpe_l1_table_from_its()
2664 if (aff != compute_its_aff(its)) in inherit_vpe_l1_table_from_its()
2668 baser = its->tables[2].val; in inherit_vpe_l1_table_from_its()
2673 gic_data_rdist()->vpe_l1_base = its->tables[2].base; in inherit_vpe_l1_table_from_its()
2693 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); in inherit_vpe_l1_table_from_its()
2711 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in inherit_vpe_l1_table_from_rd()
2723 * ours wrt CommonLPIAff. Let's use its own VPROPBASER. in inherit_vpe_l1_table_from_rd()
2729 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base; in inherit_vpe_l1_table_from_rd()
2730 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; in inherit_vpe_l1_table_from_rd()
2740 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in allocate_vpe_l2_table()
2746 if (!gic_rdists->has_rvpeid) in allocate_vpe_l2_table()
2749 /* Skip non-present CPUs */ in allocate_vpe_l2_table()
2783 table = gic_data_rdist_cpu(cpu)->vpe_l1_base; in allocate_vpe_l2_table()
2816 if (!gic_rdists->has_rvpeid) in allocate_vpe_l1_table()
2835 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2839 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC); in allocate_vpe_l1_table()
2840 if (!gic_data_rdist()->vpe_table_mask) in allocate_vpe_l1_table()
2841 return -ENOMEM; in allocate_vpe_l1_table()
2877 /* How many entries per GIC page? */ in allocate_vpe_l1_table()
2899 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); in allocate_vpe_l1_table()
2908 return -ENOMEM; in allocate_vpe_l1_table()
2910 gic_data_rdist()->vpe_l1_base = page_address(page); in allocate_vpe_l1_table()
2922 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2926 cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); in allocate_vpe_l1_table()
2931 static int its_alloc_collections(struct its_node *its) in its_alloc_collections() argument
2935 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), in its_alloc_collections()
2937 if (!its->collections) in its_alloc_collections()
2938 return -ENOMEM; in its_alloc_collections()
2941 its->collections[i].target_address = ~0ULL; in its_alloc_collections()
2957 /* Make sure the GIC will observe the zero-ed page */ in its_allocate_pending_table()
2991 * flag the RD tables as pre-allocated if the stars do align. in allocate_lpi_tables()
2995 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | in allocate_lpi_tables()
3015 return -ENOMEM; in allocate_lpi_tables()
3018 gic_data_rdist_cpu(cpu)->pend_page = pend_page; in allocate_lpi_tables()
3034 count--; in read_vpend_dirty_clear()
3041 pr_err_ratelimited("ITS virtual pending table not cleaning\n"); in read_vpend_dirty_clear()
3071 if (gic_data_rdist()->lpi_enabled) in its_cpu_init_lpis()
3075 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && in its_cpu_init_lpis()
3083 if (WARN_ON(gic_rdists->prop_table_pa != paddr)) in its_cpu_init_lpis()
3090 its_free_pending_table(gic_data_rdist()->pend_page); in its_cpu_init_lpis()
3091 gic_data_rdist()->pend_page = NULL; in its_cpu_init_lpis()
3096 pend_page = gic_data_rdist()->pend_page; in its_cpu_init_lpis()
3101 val = (gic_rdists->prop_table_pa | in its_cpu_init_lpis()
3104 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); in its_cpu_init_lpis()
3118 * The HW reports non-shareable, we must in its_cpu_init_lpis()
3127 pr_info_once("GIC: using cache flushing for LPI property table\n"); in its_cpu_init_lpis()
3128 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; in its_cpu_init_lpis()
3147 * The HW reports non-shareable, we must remove the in its_cpu_init_lpis()
3161 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { in its_cpu_init_lpis()
3168 * as out of range and dropped by GIC. in its_cpu_init_lpis()
3171 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_cpu_init_lpis()
3190 gic_rdists->has_rvpeid = false; in its_cpu_init_lpis()
3191 gic_rdists->has_vlpis = false; in its_cpu_init_lpis()
3194 /* Make sure the GIC has seen the above */ in its_cpu_init_lpis()
3197 gic_data_rdist()->lpi_enabled = true; in its_cpu_init_lpis()
3200 gic_data_rdist()->pend_page ? "allocated" : "reserved", in its_cpu_init_lpis()
3204 static void its_cpu_init_collection(struct its_node *its) in its_cpu_init_collection() argument
3209 /* avoid cross node collections and its mapping */ in its_cpu_init_collection()
3210 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { in its_cpu_init_collection()
3214 if (its->numa_node != NUMA_NO_NODE && in its_cpu_init_collection()
3215 its->numa_node != of_node_to_nid(cpu_node)) in its_cpu_init_collection()
3220 * We now have to bind each collection to its target in its_cpu_init_collection()
3223 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { in its_cpu_init_collection()
3225 * This ITS wants the physical address of the in its_cpu_init_collection()
3228 target = gic_data_rdist()->phys_base; in its_cpu_init_collection()
3230 /* This ITS wants a linear CPU number. */ in its_cpu_init_collection()
3236 its->collections[cpu].target_address = target; in its_cpu_init_collection()
3237 its->collections[cpu].col_id = cpu; in its_cpu_init_collection()
3239 its_send_mapc(its, &its->collections[cpu], 1); in its_cpu_init_collection()
3240 its_send_invall(its, &its->collections[cpu]); in its_cpu_init_collection()
3245 struct its_node *its; in its_cpu_init_collections() local
3249 list_for_each_entry(its, &its_nodes, entry) in its_cpu_init_collections()
3250 its_cpu_init_collection(its); in its_cpu_init_collections()
3255 static struct its_device *its_find_device(struct its_node *its, u32 dev_id) in its_find_device() argument
3260 raw_spin_lock_irqsave(&its->lock, flags); in its_find_device()
3262 list_for_each_entry(tmp, &its->its_device_list, entry) { in its_find_device()
3263 if (tmp->device_id == dev_id) { in its_find_device()
3269 raw_spin_unlock_irqrestore(&its->lock, flags); in its_find_device()
3274 static struct its_baser *its_get_baser(struct its_node *its, u32 type) in its_get_baser() argument
3279 if (GITS_BASER_TYPE(its->tables[i].val) == type) in its_get_baser()
3280 return &its->tables[i]; in its_get_baser()
3286 static bool its_alloc_table_entry(struct its_node *its, in its_alloc_table_entry() argument
3294 esz = GITS_BASER_ENTRY_SIZE(baser->val); in its_alloc_table_entry()
3295 if (!(baser->val & GITS_BASER_INDIRECT)) in its_alloc_table_entry()
3296 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); in its_alloc_table_entry()
3299 idx = id >> ilog2(baser->psz / esz); in its_alloc_table_entry()
3300 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) in its_alloc_table_entry()
3303 table = baser->base; in its_alloc_table_entry()
3311 page = alloc_pages_node(its->numa_node, gfp_flags, in its_alloc_table_entry()
3312 get_order(baser->psz)); in its_alloc_table_entry()
3317 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3318 gic_flush_dcache_to_poc(page_address(page), baser->psz); in its_alloc_table_entry()
3323 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3326 /* Ensure updated table contents are visible to ITS hardware */ in its_alloc_table_entry()
3333 static bool its_alloc_device_table(struct its_node *its, u32 dev_id) in its_alloc_device_table() argument
3337 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); in its_alloc_device_table()
3339 /* Don't allow device id that exceeds ITS hardware limit */ in its_alloc_device_table()
3341 return (ilog2(dev_id) < device_ids(its)); in its_alloc_device_table()
3343 return its_alloc_table_entry(its, baser, dev_id); in its_alloc_device_table()
3348 struct its_node *its; in its_alloc_vpe_table() local
3358 list_for_each_entry(its, &its_nodes, entry) { in its_alloc_vpe_table()
3361 if (!is_v4(its)) in its_alloc_vpe_table()
3364 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); in its_alloc_vpe_table()
3368 if (!its_alloc_table_entry(its, baser, vpe_id)) in its_alloc_vpe_table()
3373 if (!gic_rdists->has_rvpeid) in its_alloc_vpe_table()
3388 static struct its_device *its_create_device(struct its_node *its, u32 dev_id, in its_create_device() argument
3402 if (!its_alloc_device_table(its, dev_id)) in its_create_device()
3414 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); in its_create_device()
3415 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; in its_create_device()
3421 itt = kzalloc_node(sz, gfp_flags, its->numa_node); in its_create_device()
3451 dev->its = its; in its_create_device()
3452 dev->itt = itt; in its_create_device()
3453 dev->itt_sz = sz; in its_create_device()
3454 dev->nr_ites = nr_ites; in its_create_device()
3455 dev->event_map.lpi_map = lpi_map; in its_create_device()
3456 dev->event_map.col_map = col_map; in its_create_device()
3457 dev->event_map.lpi_base = lpi_base; in its_create_device()
3458 dev->event_map.nr_lpis = nr_lpis; in its_create_device()
3459 raw_spin_lock_init(&dev->event_map.vlpi_lock); in its_create_device()
3460 dev->device_id = dev_id; in its_create_device()
3461 INIT_LIST_HEAD(&dev->entry); in its_create_device()
3463 raw_spin_lock_irqsave(&its->lock, flags); in its_create_device()
3464 list_add(&dev->entry, &its->its_device_list); in its_create_device()
3465 raw_spin_unlock_irqrestore(&its->lock, flags); in its_create_device()
3467 /* Map device to its ITT */ in its_create_device()
3477 raw_spin_lock_irqsave(&its_dev->its->lock, flags); in its_free_device()
3478 list_del(&its_dev->entry); in its_free_device()
3479 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); in its_free_device()
3480 kfree(its_dev->event_map.col_map); in its_free_device()
3484 free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz)); in its_free_device()
3486 kfree(its_dev->itt); in its_free_device()
3496 idx = bitmap_find_free_region(dev->event_map.lpi_map, in its_alloc_device_irq()
3497 dev->event_map.nr_lpis, in its_alloc_device_irq()
3500 return -ENOSPC; in its_alloc_device_irq()
3502 *hwirq = dev->event_map.lpi_base + idx; in its_alloc_device_irq()
3510 struct its_node *its; in its_msi_prepare() local
3520 * are built on top of the ITS. in its_msi_prepare()
3522 dev_id = info->scratchpad[0].ul; in its_msi_prepare()
3525 its = msi_info->data; in its_msi_prepare()
3527 if (!gic_rdists->has_direct_lpi && in its_msi_prepare()
3529 vpe_proxy.dev->its == its && in its_msi_prepare()
3530 dev_id == vpe_proxy.dev->device_id) { in its_msi_prepare()
3534 return -EINVAL; in its_msi_prepare()
3537 mutex_lock(&its->dev_alloc_lock); in its_msi_prepare()
3538 its_dev = its_find_device(its, dev_id); in its_msi_prepare()
3545 its_dev->shared = true; in its_msi_prepare()
3550 its_dev = its_create_device(its, dev_id, nvec, true); in its_msi_prepare()
3552 err = -ENOMEM; in its_msi_prepare()
3558 mutex_unlock(&its->dev_alloc_lock); in its_msi_prepare()
3559 info->scratchpad[0].ptr = its_dev; in its_msi_prepare()
3573 if (irq_domain_get_of_node(domain->parent)) { in its_irq_gic_domain_alloc()
3574 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3579 } else if (is_fwnode_irqchip(domain->parent->fwnode)) { in its_irq_gic_domain_alloc()
3580 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3585 return -EINVAL; in its_irq_gic_domain_alloc()
3595 struct its_device *its_dev = info->scratchpad[0].ptr; in its_irq_domain_alloc()
3596 struct its_node *its = its_dev->its; in its_irq_domain_alloc() local
3606 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); in its_irq_domain_alloc()
3621 (int)(hwirq + i - its_dev->event_map.lpi_base), in its_irq_domain_alloc()
3637 return -EINVAL; in its_irq_domain_activate()
3640 its_dev->event_map.col_map[event] = cpu; in its_irq_domain_activate()
3643 /* Map the GIC IRQ and event to the device */ in its_irq_domain_activate()
3644 its_send_mapti(its_dev, d->hwirq, event); in its_irq_domain_activate()
3654 its_dec_lpi_count(d, its_dev->event_map.col_map[event]); in its_irq_domain_deactivate()
3664 struct its_node *its = its_dev->its; in its_irq_domain_free() local
3667 bitmap_release_region(its_dev->event_map.lpi_map, in its_irq_domain_free()
3678 mutex_lock(&its->dev_alloc_lock); in its_irq_domain_free()
3684 if (!its_dev->shared && in its_irq_domain_free()
3685 bitmap_empty(its_dev->event_map.lpi_map, in its_irq_domain_free()
3686 its_dev->event_map.nr_lpis)) { in its_irq_domain_free()
3687 its_lpi_free(its_dev->event_map.lpi_map, in its_irq_domain_free()
3688 its_dev->event_map.lpi_base, in its_irq_domain_free()
3689 its_dev->event_map.nr_lpis); in its_irq_domain_free()
3696 mutex_unlock(&its->dev_alloc_lock); in its_irq_domain_free()
3730 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap_locked()
3734 if (vpe->vpe_proxy_event == -1) in its_vpe_db_proxy_unmap_locked()
3737 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_db_proxy_unmap_locked()
3738 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; in its_vpe_db_proxy_unmap_locked()
3748 vpe_proxy.next_victim = vpe->vpe_proxy_event; in its_vpe_db_proxy_unmap_locked()
3750 vpe->vpe_proxy_event = -1; in its_vpe_db_proxy_unmap_locked()
3756 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap()
3759 if (!gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_unmap()
3771 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_map_locked()
3775 if (vpe->vpe_proxy_event != -1) in its_vpe_db_proxy_map_locked()
3784 vpe->vpe_proxy_event = vpe_proxy.next_victim; in its_vpe_db_proxy_map_locked()
3785 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; in its_vpe_db_proxy_map_locked()
3787 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; in its_vpe_db_proxy_map_locked()
3788 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); in its_vpe_db_proxy_map_locked()
3797 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_move()
3800 if (gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_move()
3803 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; in its_vpe_db_proxy_move()
3804 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_db_proxy_move()
3814 target_col = &vpe_proxy.dev->its->collections[to]; in its_vpe_db_proxy_move()
3815 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); in its_vpe_db_proxy_move()
3816 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; in its_vpe_db_proxy_move()
3833 * interrupt to its new location. in its_vpe_set_affinity()
3838 * protect us, and that we must ensure nobody samples vpe->col_idx in its_vpe_set_affinity()
3840 * taken on any vLPI handling path that evaluates vpe->col_idx. in its_vpe_set_affinity()
3846 vpe->col_idx = cpu; in its_vpe_set_affinity()
3850 * is sharing its VPE table with the current one. in its_vpe_set_affinity()
3852 if (gic_data_rdist_cpu(cpu)->vpe_table_mask && in its_vpe_set_affinity()
3853 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask)) in its_vpe_set_affinity()
3871 if (!gic_rdists->has_vpend_valid_dirty) in its_wait_vpt_parse_complete()
3886 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & in its_vpe_schedule()
3888 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_vpe_schedule()
3893 val = virt_to_phys(page_address(vpe->vpt_page)) & in its_vpe_schedule()
3900 * easily. So in the end, vpe->pending_last is only an in its_vpe_schedule()
3903 * would be able to read its coarse map pretty quickly anyway, in its_vpe_schedule()
3907 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; in its_vpe_schedule()
3919 vpe->idai = !!(val & GICR_VPENDBASER_IDAI); in its_vpe_deschedule()
3920 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_deschedule()
3925 struct its_node *its; in its_vpe_invall() local
3927 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_invall()
3928 if (!is_v4(its)) in its_vpe_invall()
3931 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) in its_vpe_invall()
3935 * Sending a VINVALL to a single ITS is enough, as all in its_vpe_invall()
3938 its_send_vinvall(its, vpe); in its_vpe_invall()
3948 switch (info->cmd_type) { in its_vpe_set_vcpu_affinity()
3966 return -EINVAL; in its_vpe_set_vcpu_affinity()
3978 cmd(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_send_cmd()
3987 if (gic_rdists->has_direct_lpi) { in its_vpe_send_inv()
3991 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); in its_vpe_send_inv()
3992 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; in its_vpe_send_inv()
3993 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); in its_vpe_send_inv()
3995 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); in its_vpe_send_inv()
4009 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_mask_irq()
4016 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_unmask_irq()
4027 return -EINVAL; in its_vpe_set_irqchip_state()
4029 if (gic_rdists->has_direct_lpi) { in its_vpe_set_irqchip_state()
4032 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; in its_vpe_set_irqchip_state()
4034 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); in its_vpe_set_irqchip_state()
4036 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_set_irqchip_state()
4055 .name = "GICv4-vpe",
4067 static struct its_node *its = NULL; in find_4_1_its() local
4069 if (!its) { in find_4_1_its()
4070 list_for_each_entry(its, &its_nodes, entry) { in find_4_1_its()
4071 if (is_v4_1(its)) in find_4_1_its()
4072 return its; in find_4_1_its()
4076 its = NULL; in find_4_1_its()
4079 return its; in find_4_1_its()
4085 struct its_node *its; in its_vpe_4_1_send_inv() local
4090 * it to the first valid ITS, and let the HW do its magic. in its_vpe_4_1_send_inv()
4092 its = find_4_1_its(); in its_vpe_4_1_send_inv()
4093 if (its) in its_vpe_4_1_send_inv()
4094 its_send_invdb(its, vpe); in its_vpe_4_1_send_inv()
4099 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_4_1_mask_irq()
4105 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_4_1_unmask_irq()
4117 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0; in its_vpe_4_1_schedule()
4118 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0; in its_vpe_4_1_schedule()
4119 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id); in its_vpe_4_1_schedule()
4130 if (info->req_db) { in its_vpe_4_1_deschedule()
4134 * vPE is going to block: make the vPE non-resident with in its_vpe_4_1_deschedule()
4135 * PendingLast clear and DB set. The GIC guarantees that if in its_vpe_4_1_deschedule()
4136 * we read-back PendingLast clear, then a doorbell will be in its_vpe_4_1_deschedule()
4143 raw_spin_lock_irqsave(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4147 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_4_1_deschedule()
4148 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4151 * We're not blocking, so just make the vPE non-resident in its_vpe_4_1_deschedule()
4157 vpe->pending_last = true; in its_vpe_4_1_deschedule()
4169 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); in its_vpe_4_1_invall()
4173 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall()
4174 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in its_vpe_4_1_invall()
4178 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall()
4187 switch (info->cmd_type) { in its_vpe_4_1_set_vcpu_affinity()
4205 return -EINVAL; in its_vpe_4_1_set_vcpu_affinity()
4210 .name = "GICv4.1-vpe",
4224 desc.its_vsgi_cmd.sgi = d->hwirq; in its_configure_sgi()
4225 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; in its_configure_sgi()
4226 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; in its_configure_sgi()
4227 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; in its_configure_sgi()
4231 * GICv4.1 allows us to send VSGI commands to any ITS as long as the in its_configure_sgi()
4233 * activation time, we're pretty sure the first GICv4.1 ITS will do. in its_configure_sgi()
4242 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_mask_irq()
4250 vpe->sgi_config[d->hwirq].enabled = true; in its_sgi_unmask_irq()
4272 return -EINVAL; in its_sgi_set_irqchip_state()
4276 struct its_node *its = find_4_1_its(); in its_sgi_set_irqchip_state() local
4279 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); in its_sgi_set_irqchip_state()
4280 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); in its_sgi_set_irqchip_state()
4281 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); in its_sgi_set_irqchip_state()
4300 return -EINVAL; in its_sgi_get_irqchip_state()
4305 * - Concurent vPE affinity change: we must make sure it cannot in its_sgi_get_irqchip_state()
4309 * - Concurrent VSGIPENDR access: As it involves accessing two in its_sgi_get_irqchip_state()
4313 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4314 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; in its_sgi_get_irqchip_state()
4315 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); in its_sgi_get_irqchip_state()
4321 count--; in its_sgi_get_irqchip_state()
4331 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4335 return -ENXIO; in its_sgi_get_irqchip_state()
4337 *val = !!(status & (1 << d->hwirq)); in its_sgi_get_irqchip_state()
4347 switch (info->cmd_type) { in its_sgi_set_vcpu_affinity()
4349 vpe->sgi_config[d->hwirq].priority = info->priority; in its_sgi_set_vcpu_affinity()
4350 vpe->sgi_config[d->hwirq].group = info->group; in its_sgi_set_vcpu_affinity()
4355 return -EINVAL; in its_sgi_set_vcpu_affinity()
4360 .name = "GICv4.1-sgi",
4380 vpe->sgi_config[i].priority = 0; in its_sgi_irq_domain_alloc()
4381 vpe->sgi_config[i].enabled = false; in its_sgi_irq_domain_alloc()
4382 vpe->sgi_config[i].group = false; in its_sgi_irq_domain_alloc()
4415 * - To change the configuration, CLEAR must be set to false, in its_sgi_irq_domain_deactivate()
4417 * - To clear the pending bit, CLEAR must be set to true, leaving in its_sgi_irq_domain_deactivate()
4422 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_irq_domain_deactivate()
4458 return -ENOMEM; in its_vpe_init()
4464 return -ENOMEM; in its_vpe_init()
4467 raw_spin_lock_init(&vpe->vpe_lock); in its_vpe_init()
4468 vpe->vpe_id = vpe_id; in its_vpe_init()
4469 vpe->vpt_page = vpt_page; in its_vpe_init()
4470 if (gic_rdists->has_rvpeid) in its_vpe_init()
4471 atomic_set(&vpe->vmapp_count, 0); in its_vpe_init()
4473 vpe->vpe_proxy_event = -1; in its_vpe_init()
4481 its_vpe_id_free(vpe->vpe_id); in its_vpe_teardown()
4482 its_free_pending_table(vpe->vpt_page); in its_vpe_teardown()
4489 struct its_vm *vm = domain->host_data; in its_vpe_irq_domain_free()
4499 BUG_ON(vm != vpe->its_vm); in its_vpe_irq_domain_free()
4501 clear_bit(data->hwirq, vm->db_bitmap); in its_vpe_irq_domain_free()
4506 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { in its_vpe_irq_domain_free()
4507 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); in its_vpe_irq_domain_free()
4508 its_free_prop_table(vm->vprop_page); in its_vpe_irq_domain_free()
4525 return -ENOMEM; in its_vpe_irq_domain_alloc()
4529 return -ENOMEM; in its_vpe_irq_domain_alloc()
4535 return -ENOMEM; in its_vpe_irq_domain_alloc()
4538 vm->db_bitmap = bitmap; in its_vpe_irq_domain_alloc()
4539 vm->db_lpi_base = base; in its_vpe_irq_domain_alloc()
4540 vm->nr_db_lpis = nr_ids; in its_vpe_irq_domain_alloc()
4541 vm->vprop_page = vprop_page; in its_vpe_irq_domain_alloc()
4543 if (gic_rdists->has_rvpeid) in its_vpe_irq_domain_alloc()
4547 vm->vpes[i]->vpe_db_lpi = base + i; in its_vpe_irq_domain_alloc()
4548 err = its_vpe_init(vm->vpes[i]); in its_vpe_irq_domain_alloc()
4552 vm->vpes[i]->vpe_db_lpi); in its_vpe_irq_domain_alloc()
4556 irqchip, vm->vpes[i]); in its_vpe_irq_domain_alloc()
4575 struct its_node *its; in its_vpe_irq_domain_activate() local
4586 vpe->col_idx = cpumask_first(cpu_online_mask); in its_vpe_irq_domain_activate()
4588 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_irq_domain_activate()
4589 if (!is_v4(its)) in its_vpe_irq_domain_activate()
4592 its_send_vmapp(its, vpe, true); in its_vpe_irq_domain_activate()
4593 its_send_vinvall(its, vpe); in its_vpe_irq_domain_activate()
4596 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_vpe_irq_domain_activate()
4605 struct its_node *its; in its_vpe_irq_domain_deactivate() local
4614 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_irq_domain_deactivate()
4615 if (!is_v4(its)) in its_vpe_irq_domain_deactivate()
4618 its_send_vmapp(its, vpe, false); in its_vpe_irq_domain_deactivate()
4636 * GIC architecture specification requires the ITS to be both in its_force_quiescent()
4643 /* Disable the generation of all interrupts to this ITS */ in its_force_quiescent()
4647 /* Poll GITS_CTLR and wait until ITS becomes quiescent */ in its_force_quiescent()
4653 count--; in its_force_quiescent()
4655 return -EBUSY; in its_force_quiescent()
4664 struct its_node *its = data; in its_enable_quirk_cavium_22375() local
4667 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_cavium_22375()
4668 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); in its_enable_quirk_cavium_22375()
4669 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; in its_enable_quirk_cavium_22375()
4676 struct its_node *its = data; in its_enable_quirk_cavium_23144() local
4678 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; in its_enable_quirk_cavium_23144()
4685 struct its_node *its = data; in its_enable_quirk_qdf2400_e0065() local
4688 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; in its_enable_quirk_qdf2400_e0065()
4689 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); in its_enable_quirk_qdf2400_e0065()
4696 struct its_node *its = its_dev->its; in its_irq_get_msi_base_pre_its() local
4699 * The Socionext Synquacer SoC has a so-called 'pre-ITS', in its_irq_get_msi_base_pre_its()
4700 * which maps 32-bit writes targeted at a separate window of in its_irq_get_msi_base_pre_its()
4705 return its->pre_its_base + (its_dev->device_id << 2); in its_irq_get_msi_base_pre_its()
4710 struct its_node *its = data; in its_enable_quirk_socionext_synquacer() local
4714 if (!fwnode_property_read_u32_array(its->fwnode_handle, in its_enable_quirk_socionext_synquacer()
4715 "socionext,synquacer-pre-its", in its_enable_quirk_socionext_synquacer()
4719 its->pre_its_base = pre_its_window[0]; in its_enable_quirk_socionext_synquacer()
4720 its->get_msi_base = its_irq_get_msi_base_pre_its; in its_enable_quirk_socionext_synquacer()
4722 ids = ilog2(pre_its_window[1]) - 2; in its_enable_quirk_socionext_synquacer()
4723 if (device_ids(its) > ids) { in its_enable_quirk_socionext_synquacer()
4724 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_socionext_synquacer()
4725 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); in its_enable_quirk_socionext_synquacer()
4728 /* the pre-ITS breaks isolation, so disable MSI remapping */ in its_enable_quirk_socionext_synquacer()
4729 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; in its_enable_quirk_socionext_synquacer()
4737 struct its_node *its = data; in its_enable_quirk_hip07_161600802() local
4743 its->vlpi_redist_offset = SZ_128K; in its_enable_quirk_hip07_161600802()
4750 .desc = "ITS: Cavium errata 22375, 24313",
4758 .desc = "ITS: Cavium erratum 23144",
4766 .desc = "ITS: QDF2400 erratum 0065",
4767 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4775 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4776 * implementation, but with a 'pre-ITS' added that requires
4779 .desc = "ITS: Socionext Synquacer pre-ITS",
4787 .desc = "ITS: Hip07 erratum 161600802",
4797 static void its_enable_quirks(struct its_node *its) in its_enable_quirks() argument
4799 u32 iidr = readl_relaxed(its->base + GITS_IIDR); in its_enable_quirks()
4801 gic_enable_quirks(iidr, its_quirks, its); in its_enable_quirks()
4806 struct its_node *its; in its_save_disable() local
4810 list_for_each_entry(its, &its_nodes, entry) { in its_save_disable()
4813 base = its->base; in its_save_disable()
4814 its->ctlr_save = readl_relaxed(base + GITS_CTLR); in its_save_disable()
4817 pr_err("ITS@%pa: failed to quiesce: %d\n", in its_save_disable()
4818 &its->phys_base, err); in its_save_disable()
4819 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4823 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); in its_save_disable()
4828 list_for_each_entry_continue_reverse(its, &its_nodes, entry) { in its_save_disable()
4831 base = its->base; in its_save_disable()
4832 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4842 struct its_node *its; in its_restore_enable() local
4846 list_for_each_entry(its, &its_nodes, entry) { in its_restore_enable()
4850 base = its->base; in its_restore_enable()
4853 * Make sure that the ITS is disabled. If it fails to quiesce, in its_restore_enable()
4855 * registers is undefined according to the GIC v3 ITS in its_restore_enable()
4858 * Firmware resuming with the ITS enabled is terminally broken. in its_restore_enable()
4863 pr_err("ITS@%pa: failed to quiesce on resume: %d\n", in its_restore_enable()
4864 &its->phys_base, ret); in its_restore_enable()
4868 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); in its_restore_enable()
4874 its->cmd_write = its->cmd_base; in its_restore_enable()
4879 struct its_baser *baser = &its->tables[i]; in its_restore_enable()
4881 if (!(baser->val & GITS_BASER_VALID)) in its_restore_enable()
4884 its_write_baser(its, baser, baser->val); in its_restore_enable()
4886 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_restore_enable()
4889 * Reinit the collection if it's stored in the ITS. This is in its_restore_enable()
4891 * CID < HCC as specified in the GIC v3 Documentation. in its_restore_enable()
4893 if (its->collections[smp_processor_id()].col_id < in its_restore_enable()
4895 its_cpu_init_collection(its); in its_restore_enable()
4905 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) in its_init_domain() argument
4912 return -ENOMEM; in its_init_domain()
4914 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); in its_init_domain()
4917 return -ENOMEM; in its_init_domain()
4920 inner_domain->parent = its_parent; in its_init_domain()
4922 inner_domain->flags |= its->msi_domain_flags; in its_init_domain()
4923 info->ops = &its_msi_domain_ops; in its_init_domain()
4924 info->data = its; in its_init_domain()
4925 inner_domain->host_data = info; in its_init_domain()
4932 struct its_node *its; in its_init_vpe_domain() local
4936 if (gic_rdists->has_direct_lpi) { in its_init_vpe_domain()
4937 pr_info("ITS: Using DirectLPI for VPE invalidation\n"); in its_init_vpe_domain()
4941 /* Any ITS will do, even if not v4 */ in its_init_vpe_domain()
4942 its = list_first_entry(&its_nodes, struct its_node, entry); in its_init_vpe_domain()
4948 pr_err("ITS: Can't allocate GICv4 proxy device array\n"); in its_init_vpe_domain()
4949 return -ENOMEM; in its_init_vpe_domain()
4953 devid = GENMASK(device_ids(its) - 1, 0); in its_init_vpe_domain()
4954 vpe_proxy.dev = its_create_device(its, devid, entries, false); in its_init_vpe_domain()
4957 pr_err("ITS: Can't allocate GICv4 proxy device\n"); in its_init_vpe_domain()
4958 return -ENOMEM; in its_init_vpe_domain()
4961 BUG_ON(entries > vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
4965 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", in its_init_vpe_domain()
4966 devid, vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
4979 * guaranteed to be single-threaded, hence no in its_compute_its_list_map()
4985 pr_err("ITS@%pa: No ITSList entry available!\n", in its_compute_its_list_map()
4986 &res->start); in its_compute_its_list_map()
4987 return -EINVAL; in its_compute_its_list_map()
5001 pr_err("ITS@%pa: Duplicate ITSList entry %d\n", in its_compute_its_list_map()
5002 &res->start, its_number); in its_compute_its_list_map()
5003 return -EINVAL; in its_compute_its_list_map()
5012 struct its_node *its; in its_probe_one() local
5020 its_base = ioremap(res->start, SZ_64K); in its_probe_one()
5022 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); in its_probe_one()
5023 return -ENOMEM; in its_probe_one()
5028 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); in its_probe_one()
5029 err = -ENODEV; in its_probe_one()
5035 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); in its_probe_one()
5039 pr_info("ITS %pR\n", res); in its_probe_one()
5041 its = kzalloc(sizeof(*its), GFP_KERNEL); in its_probe_one()
5042 if (!its) { in its_probe_one()
5043 err = -ENOMEM; in its_probe_one()
5047 raw_spin_lock_init(&its->lock); in its_probe_one()
5048 mutex_init(&its->dev_alloc_lock); in its_probe_one()
5049 INIT_LIST_HEAD(&its->entry); in its_probe_one()
5050 INIT_LIST_HEAD(&its->its_device_list); in its_probe_one()
5052 its->typer = typer; in its_probe_one()
5053 its->base = its_base; in its_probe_one()
5054 its->phys_base = res->start; in its_probe_one()
5055 if (is_v4(its)) { in its_probe_one()
5061 its->list_nr = err; in its_probe_one()
5063 pr_info("ITS@%pa: Using ITS number %d\n", in its_probe_one()
5064 &res->start, err); in its_probe_one()
5066 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); in its_probe_one()
5069 if (is_v4_1(its)) { in its_probe_one()
5072 its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K); in its_probe_one()
5073 if (!its->sgir_base) { in its_probe_one()
5074 err = -ENOMEM; in its_probe_one()
5078 its->mpidr = readl_relaxed(its_base + GITS_MPIDR); in its_probe_one()
5080 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", in its_probe_one()
5081 &res->start, its->mpidr, svpet); in its_probe_one()
5085 its->numa_node = numa_node; in its_probe_one()
5090 page = alloc_pages_node(its->numa_node, gfp_flags, in its_probe_one()
5093 err = -ENOMEM; in its_probe_one()
5096 its->cmd_base = (void *)page_address(page); in its_probe_one()
5097 its->cmd_write = its->cmd_base; in its_probe_one()
5098 its->fwnode_handle = handle; in its_probe_one()
5099 its->get_msi_base = its_irq_get_msi_base; in its_probe_one()
5100 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; in its_probe_one()
5102 its_enable_quirks(its); in its_probe_one()
5104 err = its_alloc_tables(its); in its_probe_one()
5108 err = its_alloc_collections(its); in its_probe_one()
5112 baser = (virt_to_phys(its->cmd_base) | in its_probe_one()
5115 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | in its_probe_one()
5118 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5119 tmp = gits_read_cbaser(its->base + GITS_CBASER); in its_probe_one()
5130 * The HW reports non-shareable, we must in its_probe_one()
5137 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5139 pr_info("ITS: using cache flushing for cmd queue\n"); in its_probe_one()
5140 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; in its_probe_one()
5143 gits_write_cwriter(0, its->base + GITS_CWRITER); in its_probe_one()
5144 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_probe_one()
5146 if (is_v4(its)) in its_probe_one()
5148 writel_relaxed(ctlr, its->base + GITS_CTLR); in its_probe_one()
5150 err = its_init_domain(handle, its); in its_probe_one()
5155 list_add(&its->entry, &its_nodes); in its_probe_one()
5161 its_free_tables(its); in its_probe_one()
5163 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); in its_probe_one()
5165 if (its->sgir_base) in its_probe_one()
5166 iounmap(its->sgir_base); in its_probe_one()
5168 kfree(its); in its_probe_one()
5171 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); in its_probe_one()
5188 return -ENXIO; in redist_disable_lpis()
5197 * LPIs before trying to re-enable them. They are already in redist_disable_lpis()
5202 if (gic_data_rdist()->lpi_enabled || in redist_disable_lpis()
5203 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) in redist_disable_lpis()
5217 /* Make sure any change to GICR_CTLR is observable by the GIC */ in redist_disable_lpis()
5229 return -ETIMEDOUT; in redist_disable_lpis()
5232 timeout--; in redist_disable_lpis()
5242 return -EBUSY; in redist_disable_lpis()
5265 { .compatible = "arm,gic-v3-its", },
5278 if (!of_property_read_bool(np, "msi-controller")) { in its_of_probe()
5279 pr_warn("%pOF: no msi-controller property, ITS ignored\n", in its_of_probe()
5289 its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); in its_of_probe()
5302 /* GIC ITS ID */
5334 return -EINVAL; in gic_acpi_parse_srat_its()
5336 if (its_affinity->header.length < sizeof(*its_affinity)) { in gic_acpi_parse_srat_its()
5337 pr_err("SRAT: Invalid header length %d in ITS affinity\n", in gic_acpi_parse_srat_its()
5338 its_affinity->header.length); in gic_acpi_parse_srat_its()
5339 return -EINVAL; in gic_acpi_parse_srat_its()
5347 node = pxm_to_node(its_affinity->proximity_domain); in gic_acpi_parse_srat_its()
5350 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); in gic_acpi_parse_srat_its()
5355 its_srat_maps[its_in_srat].its_id = its_affinity->its_id; in gic_acpi_parse_srat_its()
5357 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", in gic_acpi_parse_srat_its()
5358 its_affinity->proximity_domain, its_affinity->its_id, node); in gic_acpi_parse_srat_its()
5387 /* free the its_srat_maps after ITS probing */
5408 res.start = its_entry->base_address; in gic_acpi_parse_madt_its()
5409 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; in gic_acpi_parse_madt_its()
5414 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", in gic_acpi_parse_madt_its()
5416 return -ENOMEM; in gic_acpi_parse_madt_its()
5419 err = iort_register_domain_token(its_entry->translation_id, res.start, in gic_acpi_parse_madt_its()
5422 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", in gic_acpi_parse_madt_its()
5423 &res.start, its_entry->translation_id); in gic_acpi_parse_madt_its()
5428 acpi_get_its_numa_node(its_entry->translation_id)); in gic_acpi_parse_madt_its()
5432 iort_deregister_domain_token(its_entry->translation_id); in gic_acpi_parse_madt_its()
5453 struct its_node *its; in its_init() local
5468 pr_warn("ITS: No ITS available, not enabling LPIs\n"); in its_init()
5469 return -ENXIO; in its_init()
5476 list_for_each_entry(its, &its_nodes, entry) { in its_init()
5477 has_v4 |= is_v4(its); in its_init()
5478 has_v4_1 |= is_v4_1(its); in its_init()
5482 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) in its_init()
5483 rdists->has_rvpeid = false; in its_init()
5485 if (has_v4 & rdists->has_vlpis) { in its_init()
5495 rdists->has_vlpis = false; in its_init()
5496 pr_err("ITS: Disabling GICv4 support\n"); in its_init()