Lines Matching refs:FIELD_PREP
207 FIELD_PREP(MIPI_RX_RESET, 1)); in max96755f_mipi_dsi_rx_config()
210 FIELD_PREP(MIPI_RX_RESET, 0)); in max96755f_mipi_dsi_rx_config()
214 FIELD_PREP(NUM_LANES, ser->num_lanes - 1)); in max96755f_mipi_dsi_rx_config()
235 regmap_write(ser->regmap, 0x0385, FIELD_PREP(DPI_HSYNC_WIDTH_L, hsa)); in max96755f_mipi_dsi_rx_config()
236 regmap_write(ser->regmap, 0x0386, FIELD_PREP(DPI_VYSNC_WIDTH_L, vsa)); in max96755f_mipi_dsi_rx_config()
238 FIELD_PREP(DPI_VSYNC_WIDTH_H, (vsa >> 8)) | in max96755f_mipi_dsi_rx_config()
239 FIELD_PREP(DPI_HSYNC_WIDTH_H, (hsa >> 8))); in max96755f_mipi_dsi_rx_config()
240 regmap_write(ser->regmap, 0x03a5, FIELD_PREP(DPI_VFP_L, vfp)); in max96755f_mipi_dsi_rx_config()
242 FIELD_PREP(DPI_VBP_L, vbp) | in max96755f_mipi_dsi_rx_config()
243 FIELD_PREP(DPI_VFP_H, (vfp >> 8))); in max96755f_mipi_dsi_rx_config()
244 regmap_write(ser->regmap, 0x03a7, FIELD_PREP(DPI_VBP_H, (vbp >> 4))); in max96755f_mipi_dsi_rx_config()
245 regmap_write(ser->regmap, 0x03a8, FIELD_PREP(DPI_VACT_L, vact)); in max96755f_mipi_dsi_rx_config()
246 regmap_write(ser->regmap, 0x03a9, FIELD_PREP(DPI_VACT_H, (vact >> 8))); in max96755f_mipi_dsi_rx_config()
247 regmap_write(ser->regmap, 0x03aa, FIELD_PREP(DPI_HFP_L, hfp)); in max96755f_mipi_dsi_rx_config()
249 FIELD_PREP(DPI_HBP_L, hbp) | in max96755f_mipi_dsi_rx_config()
250 FIELD_PREP(DPI_HFP_H, (hfp >> 7))); in max96755f_mipi_dsi_rx_config()
251 regmap_write(ser->regmap, 0x03ac, FIELD_PREP(DPI_HBP_H, (hbp >> 4))); in max96755f_mipi_dsi_rx_config()
252 regmap_write(ser->regmap, 0x03ad, FIELD_PREP(DPI_HACT_L, hact)); in max96755f_mipi_dsi_rx_config()
253 regmap_write(ser->regmap, 0x03ae, FIELD_PREP(DPI_HACT_H, (hact >> 8))); in max96755f_mipi_dsi_rx_config()
265 FIELD_PREP(TX_SPLIT_MASK_B, 0) | in max96755f_bridge_pre_enable()
266 FIELD_PREP(TX_SPLIT_MASK_A, 1) | in max96755f_bridge_pre_enable()
267 FIELD_PREP(TX_STR_SEL, 0)); in max96755f_bridge_pre_enable()
270 FIELD_PREP(TX_SPLIT_MASK_B, 1) | in max96755f_bridge_pre_enable()
271 FIELD_PREP(TX_SPLIT_MASK_A, 0) | in max96755f_bridge_pre_enable()
272 FIELD_PREP(TX_STR_SEL, 1)); in max96755f_bridge_pre_enable()
275 FIELD_PREP(DV_SWP_AB, ser->dv_swp_ab) | in max96755f_bridge_pre_enable()
276 FIELD_PREP(DV_CONV, 1) | in max96755f_bridge_pre_enable()
277 FIELD_PREP(DV_SPL, 1) | in max96755f_bridge_pre_enable()
278 FIELD_PREP(DV_EN, 1)); in max96755f_bridge_pre_enable()
288 FIELD_PREP(RESET_ONESHOT, 1)); in max96755f_bridge_reset_oneshot()
305 FIELD_PREP(START_PORTAX, 1) | in max96755f_bridge_enable()
306 FIELD_PREP(START_PORTAY, 1)); in max96755f_bridge_enable()
309 FIELD_PREP(VID_TX_EN_X, 1) | in max96755f_bridge_enable()
310 FIELD_PREP(VID_TX_EN_Y, 1)); in max96755f_bridge_enable()
314 FIELD_PREP(AUTO_LINK, 0) | in max96755f_bridge_enable()
315 FIELD_PREP(LINK_CFG, SPLITTER_MODE)); in max96755f_bridge_enable()
324 FIELD_PREP(START_PORTAX, 1) | in max96755f_bridge_enable()
325 FIELD_PREP(START_PORTAY, 1)); in max96755f_bridge_enable()
327 FIELD_PREP(VID_TX_EN_X, 1)); in max96755f_bridge_enable()
331 FIELD_PREP(AUTO_LINK, 0) | in max96755f_bridge_enable()
332 FIELD_PREP(LINK_CFG, DUAL_LINK)); in max96755f_bridge_enable()
365 FIELD_PREP(VID_TX_EN_X, 0) | in max96755f_bridge_disable()
366 FIELD_PREP(VID_TX_EN_Y, 0)); in max96755f_bridge_disable()
371 FIELD_PREP(AUTO_LINK, 1) | in max96755f_bridge_disable()
372 FIELD_PREP(LINK_CFG, LINKA)); in max96755f_bridge_disable()