Lines Matching +full:0 +full:x4
29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
40 #define BOOST_PLL_CON_MASK 0xffff
41 #define BOOST_CORE_DIV_MASK 0x1f
42 #define BOOST_CORE_DIV_SHIFT 0
43 #define BOOST_BACKUP_PLL_MASK 0x3
45 #define BOOST_BACKUP_PLL_USAGE_MASK 0x1
47 #define BOOST_BACKUP_PLL_USAGE_BORROW 0
49 #define BOOST_ENABLE_MASK 0x1
50 #define BOOST_ENABLE_SHIFT 0
51 #define BOOST_RECOVERY_MASK 0x1
53 #define BOOST_SW_CTRL_MASK 0x1
55 #define BOOST_LOW_FREQ_EN_MASK 0x1
57 #define BOOST_STATIS_ENABLE_MASK 0x1
61 #define PX30_PLL_CON(x) ((x) * 0x4)
62 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
63 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
64 #define PX30_GLB_SRST_FST 0xb8
65 #define PX30_GLB_SRST_SND 0xbc
66 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
67 #define PX30_MODE_CON 0xa0
68 #define PX30_MISC_CON 0xa4
69 #define PX30_SDMMC_CON0 0x380
70 #define PX30_SDMMC_CON1 0x384
71 #define PX30_SDIO_CON0 0x388
72 #define PX30_SDIO_CON1 0x38c
73 #define PX30_EMMC_CON0 0x390
74 #define PX30_EMMC_CON1 0x394
76 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
77 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
78 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
79 #define PX30_PMU_MODE 0x0020
81 #define RV1106_TOPCRU_BASE 0x10000
82 #define RV1106_PERICRU_BASE 0x12000
83 #define RV1106_VICRU_BASE 0x14000
84 #define RV1106_NPUCRU_BASE 0x16000
85 #define RV1106_CORECRU_BASE 0x18000
86 #define RV1106_VEPUCRU_BASE 0x1A000
87 #define RV1106_VOCRU_BASE 0x1C000
88 #define RV1106_DDRCRU_BASE 0x1E000
89 #define RV1106_SUBDDRCRU_BASE 0x1F000
91 #define RV1106_VI_GRF_BASE 0x50000
92 #define RV1106_VO_GRF_BASE 0x60000
94 #define RV1106_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300)
95 #define RV1106_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800)
96 #define RV1106_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00)
97 #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
98 #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
99 #define RV1106_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
100 #define RV1106_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
101 #define RV1106_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
102 #define RV1106_GLB_SRST_FST (0xc08 + RV1106_TOPCRU_BASE)
103 #define RV1106_GLB_SRST_SND (0xc0c + RV1106_TOPCRU_BASE)
104 #define RV1106_SDIO_CON0 (0x1c + RV1106_VO_GRF_BASE)
105 #define RV1106_SDIO_CON1 (0x20 + RV1106_VO_GRF_BASE)
106 #define RV1106_SDMMC_CON0 (0x4 + RV1106_VI_GRF_BASE)
107 #define RV1106_SDMMC_CON1 (0x8 + RV1106_VI_GRF_BASE)
108 #define RV1106_EMMC_CON0 (0x20)
109 #define RV1106_EMMC_CON1 (0x24)
110 #define RV1106_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
111 #define RV1106_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
112 #define RV1106_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
113 #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
114 #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
115 #define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
116 #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
117 #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
118 #define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
119 #define RV1106_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
120 #define RV1106_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
121 #define RV1106_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
122 #define RV1106_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
123 #define RV1106_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
124 #define RV1106_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
125 #define RV1106_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
126 #define RV1106_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
127 #define RV1106_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
128 #define RV1106_VOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
129 #define RV1106_VOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
130 #define RV1106_VOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
131 #define RV1106_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
132 #define RV1106_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
133 #define RV1106_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
134 #define RV1106_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
135 #define RV1106_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
136 #define RV1106_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
137 #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
139 #define RV1108_PLL_CON(x) ((x) * 0x4)
140 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
141 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
142 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
143 #define RV1108_GLB_SRST_FST 0x1c0
144 #define RV1108_GLB_SRST_SND 0x1c4
145 #define RV1108_MISC_CON 0x1cc
146 #define RV1108_SDMMC_CON0 0x1d8
147 #define RV1108_SDMMC_CON1 0x1dc
148 #define RV1108_SDIO_CON0 0x1e0
149 #define RV1108_SDIO_CON1 0x1e4
150 #define RV1108_EMMC_CON0 0x1e8
151 #define RV1108_EMMC_CON1 0x1ec
153 #define RV1126_PMU_MODE 0x0
154 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
155 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
156 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
157 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
158 #define RV1126_PLL_CON(x) ((x) * 0x4)
159 #define RV1126_MODE_CON 0x90
160 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
161 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
162 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
163 #define RV1126_GLB_SRST_FST 0x408
164 #define RV1126_GLB_SRST_SND 0x40c
165 #define RV1126_SDMMC_CON0 0x440
166 #define RV1126_SDMMC_CON1 0x444
167 #define RV1126_SDIO_CON0 0x448
168 #define RV1126_SDIO_CON1 0x44c
169 #define RV1126_EMMC_CON0 0x450
170 #define RV1126_EMMC_CON1 0x454
177 #define RK1808_PLL_CON(x) ((x) * 0x4)
178 #define RK1808_MODE_CON 0xa0
179 #define RK1808_MISC_CON 0xa4
180 #define RK1808_MISC1_CON 0xa8
181 #define RK1808_GLB_SRST_FST 0xb8
182 #define RK1808_GLB_SRST_SND 0xbc
183 #define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
184 #define RK1808_CLKGATE_CON(x) ((x) * 0x4 + 0x230)
185 #define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
186 #define RK1808_SDMMC_CON0 0x380
187 #define RK1808_SDMMC_CON1 0x384
188 #define RK1808_SDIO_CON0 0x388
189 #define RK1808_SDIO_CON1 0x38c
190 #define RK1808_EMMC_CON0 0x390
191 #define RK1808_EMMC_CON1 0x394
193 #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000)
194 #define RK1808_PMU_MODE_CON 0x4020
195 #define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x4040)
196 #define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x4080)
198 #define RK2928_PLL_CON(x) ((x) * 0x4)
199 #define RK2928_MODE_CON 0x40
200 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
201 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
202 #define RK2928_GLB_SRST_FST 0x100
203 #define RK2928_GLB_SRST_SND 0x104
204 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
205 #define RK2928_MISC_CON 0x134
207 #define RK3036_SDMMC_CON0 0x144
208 #define RK3036_SDMMC_CON1 0x148
209 #define RK3036_SDIO_CON0 0x14c
210 #define RK3036_SDIO_CON1 0x150
211 #define RK3036_EMMC_CON0 0x154
212 #define RK3036_EMMC_CON1 0x158
214 #define RK3228_GLB_SRST_FST 0x1f0
215 #define RK3228_GLB_SRST_SND 0x1f4
216 #define RK3228_SDMMC_CON0 0x1c0
217 #define RK3228_SDMMC_CON1 0x1c4
218 #define RK3228_SDIO_CON0 0x1c8
219 #define RK3228_SDIO_CON1 0x1cc
220 #define RK3228_EMMC_CON0 0x1d8
221 #define RK3228_EMMC_CON1 0x1dc
224 #define RK3288_MODE_CON 0x50
225 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
226 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
227 #define RK3288_GLB_SRST_FST 0x1b0
228 #define RK3288_GLB_SRST_SND 0x1b4
229 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
230 #define RK3288_MISC_CON 0x1e8
231 #define RK3288_SDMMC_CON0 0x200
232 #define RK3288_SDMMC_CON1 0x204
233 #define RK3288_SDIO0_CON0 0x208
234 #define RK3288_SDIO0_CON1 0x20c
235 #define RK3288_SDIO1_CON0 0x210
236 #define RK3288_SDIO1_CON1 0x214
237 #define RK3288_EMMC_CON0 0x218
238 #define RK3288_EMMC_CON1 0x21c
241 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
242 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
243 #define RK3308_GLB_SRST_FST 0xb8
244 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
245 #define RK3308_MODE_CON 0xa0
246 #define RK3308_SDMMC_CON0 0x480
247 #define RK3308_SDMMC_CON1 0x484
248 #define RK3308_SDIO_CON0 0x488
249 #define RK3308_SDIO_CON1 0x48c
250 #define RK3308_EMMC_CON0 0x490
251 #define RK3308_EMMC_CON1 0x494
254 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
255 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
256 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
257 #define RK3328_GLB_SRST_FST 0x9c
258 #define RK3328_GLB_SRST_SND 0x98
259 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
260 #define RK3328_MODE_CON 0x80
261 #define RK3328_MISC_CON 0x84
262 #define RK3328_SDMMC_CON0 0x380
263 #define RK3328_SDMMC_CON1 0x384
264 #define RK3328_SDIO_CON0 0x388
265 #define RK3328_SDIO_CON1 0x38c
266 #define RK3328_EMMC_CON0 0x390
267 #define RK3328_EMMC_CON1 0x394
268 #define RK3328_SDMMC_EXT_CON0 0x398
269 #define RK3328_SDMMC_EXT_CON1 0x39C
272 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
273 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
274 #define RK3368_GLB_SRST_FST 0x280
275 #define RK3368_GLB_SRST_SND 0x284
276 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
277 #define RK3368_MISC_CON 0x380
278 #define RK3368_SDMMC_CON0 0x400
279 #define RK3368_SDMMC_CON1 0x404
280 #define RK3368_SDIO0_CON0 0x408
281 #define RK3368_SDIO0_CON1 0x40c
282 #define RK3368_SDIO1_CON0 0x410
283 #define RK3368_SDIO1_CON1 0x414
284 #define RK3368_EMMC_CON0 0x418
285 #define RK3368_EMMC_CON1 0x41c
288 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
289 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
290 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
291 #define RK3399_GLB_SRST_FST 0x500
292 #define RK3399_GLB_SRST_SND 0x504
293 #define RK3399_GLB_CNT_TH 0x508
294 #define RK3399_MISC_CON 0x50c
295 #define RK3399_RST_CON 0x510
296 #define RK3399_RST_ST 0x514
297 #define RK3399_SDMMC_CON0 0x580
298 #define RK3399_SDMMC_CON1 0x584
299 #define RK3399_SDIO_CON0 0x588
300 #define RK3399_SDIO_CON1 0x58c
303 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
304 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
305 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
307 #define RK3528_PMU_CRU_BASE 0x10000
308 #define RK3528_PCIE_CRU_BASE 0x20000
309 #define RK3528_DDRPHY_CRU_BASE 0x28000
310 #define RK3528_VPU_GRF_BASE 0x40000
311 #define RK3528_VO_GRF_BASE 0x60000
312 #define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24)
313 #define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28)
314 #define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4)
315 #define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8)
316 #define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc)
317 #define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10)
319 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
320 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
321 #define RK3528_MODE_CON 0x280
322 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
323 #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
324 #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
325 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
326 #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
327 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
328 #define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
329 #define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
330 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
331 #define RK3528_GLB_CNT_TH 0xc00
332 #define RK3528_GLB_SRST_FST 0xc08
333 #define RK3528_GLB_SRST_SND 0xc0c
335 #define RK3562_PMU0_CRU_BASE 0x10000
336 #define RK3562_PMU1_CRU_BASE 0x18000
337 #define RK3562_DDR_CRU_BASE 0x20000
338 #define RK3562_SUBDDR_CRU_BASE 0x28000
339 #define RK3562_PERI_CRU_BASE 0x30000
342 #define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
343 #define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
344 #define RK3562_MODE_CON 0x600
345 #define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
346 #define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
347 #define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
348 #define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
349 #define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
350 #define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
351 #define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
352 #define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
353 #define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
354 #define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
355 #define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
356 #define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
357 #define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
358 #define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
359 #define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
360 #define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
361 #define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
362 #define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
363 #define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
364 #define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
365 #define RK3562_GLB_SRST_FST 0x614
366 #define RK3562_GLB_SRST_SND 0x618
367 #define RK3562_GLB_RST_CON 0x61c
368 #define RK3562_GLB_RST_ST 0x620
369 #define RK3562_SDMMC0_CON0 0x624
370 #define RK3562_SDMMC0_CON1 0x628
371 #define RK3562_SDMMC1_CON0 0x62c
372 #define RK3562_SDMMC1_CON1 0x630
375 #define RK3568_MODE_CON0 0xc0
376 #define RK3568_MISC_CON0 0xc4
377 #define RK3568_MISC_CON1 0xc8
378 #define RK3568_MISC_CON2 0xcc
379 #define RK3568_GLB_CNT_TH 0xd0
380 #define RK3568_GLB_SRST_FST 0xd4
381 #define RK3568_GLB_SRST_SND 0xd8
382 #define RK3568_GLB_RST_CON 0xdc
383 #define RK3568_GLB_RST_ST 0xe0
384 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
385 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
386 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
387 #define RK3568_SDMMC0_CON0 0x580
388 #define RK3568_SDMMC0_CON1 0x584
389 #define RK3568_SDMMC1_CON0 0x588
390 #define RK3568_SDMMC1_CON1 0x58c
391 #define RK3568_SDMMC2_CON0 0x590
392 #define RK3568_SDMMC2_CON1 0x594
393 #define RK3568_EMMC_CON0 0x598
394 #define RK3568_EMMC_CON1 0x59c
397 #define RK3568_PMU_MODE_CON0 0x80
398 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
399 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
400 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
402 #define RK3588_PHP_CRU_BASE 0x8000
403 #define RK3588_PMU_CRU_BASE 0x30000
404 #define RK3588_BIGCORE0_CRU_BASE 0x50000
405 #define RK3588_BIGCORE1_CRU_BASE 0x52000
406 #define RK3588_DSU_CRU_BASE 0x58000
409 #define RK3588_MODE_CON0 0x280
410 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
411 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
412 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
413 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
414 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
415 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
416 #define RK3588_GLB_CNT_TH 0xc00
417 #define RK3588_GLB_SRST_FST 0xc08
418 #define RK3588_GLB_SRST_SND 0xc0c
419 #define RK3588_GLB_RST_CON 0xc10
420 #define RK3588_GLB_RST_ST 0xc04
421 #define RK3588_SDIO_CON0 0xC24
422 #define RK3588_SDIO_CON1 0xC28
423 #define RK3588_SDMMC_CON0 0xC30
424 #define RK3588_SDMMC_CON1 0xC34
426 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
427 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
429 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
430 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
431 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
432 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
434 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
435 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
436 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
437 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
438 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
439 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
440 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
441 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
442 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
443 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
444 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
445 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
578 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
681 #define ROCKCHIP_DDRCLK_SIP BIT(0)
682 #define ROCKCHIP_DDRCLK_SIP_V2 0x03
709 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
1254 FACTOR(_id, cname, pname, 0, 1, 1)
1286 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)