Lines Matching refs:DFLAGS
256 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
325 RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
337 RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
350 RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
362 RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
367 RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
375 RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
382 RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
388 RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
405 RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
419 RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
459 RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
468 RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
476 RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
481 RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
486 RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
502 RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
516 RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
527 RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
538 RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
550 DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
561 DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
572 RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
577 RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
582 RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
587 RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
593 RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
601 RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
628 RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
654 RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
660 RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
669 RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
676 RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
686 RV1126_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
689 RV1126_CLKSEL_CON(4), 8, 5, DFLAGS,
696 RV1126_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 5, DFLAGS,
699 RV1126_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 5, DFLAGS,
707 RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
713 RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
722 RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
740 RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
754 RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
769 RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
775 RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
791 RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
799 RV1126_CLKSEL_CON(40), 6, 2, MFLAGS, 0, 5, DFLAGS,
802 RV1126_CLKSEL_CON(41), 0, 5, DFLAGS,
809 RV1126_CLKSEL_CON(40), 14, 2, MFLAGS, 8, 5, DFLAGS,
818 RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
821 RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
828 RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
831 RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
839 RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
842 RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
849 RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
852 RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
864 RV1126_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
867 RV1126_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
870 RV1126_CLKSEL_CON(43), 14, 2, MFLAGS, 8, 5, DFLAGS,
882 RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
885 RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
888 RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
895 RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
902 RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
917 RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
925 RV1126_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
929 RV1126_CLKSEL_CON(76), 0, 5, DFLAGS,
934 RV1126_CLKSEL_CON(49), 8, 5, DFLAGS,
937 RV1126_CLKSEL_CON(50), 8, 5, DFLAGS,
944 RV1126_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
948 RV1126_CLKSEL_CON(76), 8, 5, DFLAGS,
957 RV1126_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
960 RV1126_CLKSEL_CON(51), 15, 1, MFLAGS, 8, 6, DFLAGS,
969 RV1126_CLKSEL_CON(73), 8, 1, MFLAGS, 0, 5, DFLAGS,
984 RV1126_CLKSEL_CON(54), 14, 2, MFLAGS, 8, 5, DFLAGS,
992 RV1126_CLKSEL_CON(68), 6, 2, MFLAGS, 0, 5, DFLAGS,
996 RV1126_CLKSEL_CON(77), 0, 5, DFLAGS,
1001 RV1126_CLKSEL_CON(69), 8, 5, DFLAGS,
1008 RV1126_CLKSEL_CON(69), 6, 2, MFLAGS, 0, 5, DFLAGS,
1012 RV1126_CLKSEL_CON(77), 8, 5, DFLAGS,
1022 RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
1025 RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
1034 DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
1044 RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
1055 RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
1060 RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
1067 RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
1083 RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
1087 RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
1098 RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
1106 RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
1140 RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
1149 RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 0, 4, DFLAGS,
1152 RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 4, 4, DFLAGS,
1157 RV1126_CLKSEL_CON(66), 8, 4, DFLAGS,
1160 RV1126_CLKSEL_CON(66), 0, 5, DFLAGS,
1167 RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 0, 4, DFLAGS,
1170 RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 4, 4, DFLAGS,
1203 RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
1341 RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
1348 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS),
1350 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,