Lines Matching refs:GATE
328 GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
330 GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
341 GATE(0, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
343 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
389 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
398 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
409 GATE(MCLK_REF_MIPI0, "mclk_ref_mipi0", "clk_ref_mipi0", 0,
418 GATE(MCLK_REF_MIPI1, "mclk_ref_mipi1", "clk_ref_mipi1", 0,
427 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
436 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
445 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
454 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
463 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
472 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
481 GATE(SCLK_VICAP_M0, "sclk_vicap_m0", "clk_vicap_m0", 0,
490 GATE(SCLK_VICAP_M1, "sclk_vicap_m1", "clk_vicap_m1", 0,
503 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
505 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
507 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
509 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
511 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
513 GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
515 GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
528 GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_root", 0,
530 GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
546 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_peri_root", 0,
557 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_root", 0,
559 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri_root", 0,
561 GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_root", 0,
563 GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
568 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
570 GATE(PCLK_DSM, "pclk_dsm", "pclk_peri_root", 0,
572 GATE(MCLK_DSM, "mclk_dsm", "mclk_i2s0_8ch_tx", 0,
577 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri_root", 0,
579 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri_root", 0,
581 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
583 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri_root", 0,
588 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
593 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
598 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
603 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_peri_root", 0,
605 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_peri_root", CLK_IGNORE_UNUSED,
607 GATE(HCLK_IVE, "hclk_ive", "hclk_peri_root", 0,
609 GATE(ACLK_IVE, "aclk_ive", "aclk_peri_root", 0,
611 GATE(PCLK_PWM0_PERI, "pclk_pwm0_peri", "pclk_peri_root", 0,
616 GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
618 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
620 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri_root", 0,
625 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri_root", 0,
627 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
629 GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri_root", 0,
634 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
636 GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri_root", 0,
641 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
643 GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri_root", 0,
645 GATE(HCLK_SAI, "hclk_sai", "hclk_peri_root", 0,
647 GATE(MCLK_SAI, "mclk_sai", "mclk_i2s0_8ch_tx", 0,
649 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
654 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
659 GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
661 GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
663 GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
665 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
667 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
669 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
671 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
673 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
675 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
677 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
679 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri_root", 0,
681 GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri_root", 0,
683 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
685 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri_root", 0,
687 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri_root", 0,
689 GATE(PCLK_UART5, "pclk_uart5", "pclk_peri_root", 0,
691 GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_bus_root", 0,
693 GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
695 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_peri_root", 0,
697 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
699 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
701 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
703 GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
705 GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
721 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
723 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
725 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu", 0,
727 GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "pclk_pmu_root", 0,
732 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pmu_root", 0,
737 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
739 GATE(CLK_PMU_MCU, "clk_pmu_mcu", "hclk_pmu_root", 0,
741 GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
746 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
748 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
750 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IGNORE_UNUSED,
752 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
762 GATE(CLK_DFICTRL, "clk_dfictrl", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
764 GATE(CLK_DDRMON, "clk_ddrmon", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
766 GATE(CLK_DDR_PHY, "clk_ddr_phy", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
768 GATE(ACLK_DDRC, "aclk_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
770 GATE(CLK_CORE_DDRC, "clk_core_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
787 GATE(PCLK_SPI0, "pclk_spi0", "pclk_vepu_root", 0,
792 GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
794 GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
796 GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
804 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vepu_root", 0,
806 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
808 GATE(HCLK_VEPU_PP, "hclk_vepu_pp", "hclk_vepu_root", 0,
810 GATE(ACLK_VEPU_PP, "aclk_vepu_pp", "aclk_vepu_root", 0,
827 GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi_root", 0,
829 GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi_root", 0,
831 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vi_root", 0,
833 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
835 GATE(HCLK_ISP3P2, "hclk_isp3p2", "hclk_vi_root", 0,
837 GATE(ACLK_ISP3P2, "aclk_isp3p2", "aclk_vi_root", 0,
842 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_vi_root", 0,
847 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_vi_root", 0,
849 GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
851 GATE(PCLK_VI_RTC_TEST, "pclk_vi_rtc_test", "pclk_vi_rtc_root", 0,
853 GATE(PCLK_VI_RTC_PHY, "pclk_vi_rtc_phy", "pclk_vi_rtc_root", 0,
858 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
860 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
880 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
882 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
884 GATE(ACLK_MAC, "aclk_mac", "aclk_mac_root", 0,
886 GATE(PCLK_MAC, "pclk_mac", "pclk_vo_root", 0,
892 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
894 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
896 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
898 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
903 GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
905 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
910 GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
912 GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
914 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
916 GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
924 GATE(HCLK_SDIO, "hclk_sdio", "hclk_vo_root", 0,
926 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vo_root", 0,
934 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
936 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_src", 0,
938 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
942 GATE(RX0PCLK_VICAP, "rx0pclk_vicap", "rx0pclk_vicap_io", 0,
944 GATE(RX1PCLK_VICAP, "rx1pclk_vicap", "rx1pclk_vicap_io", 0,
946 GATE(ISP0CLK_VICAP, "isp0clk_vicap", "isp0clk_vicap_io", 0,
948 GATE(I0CLK_VICAP, "i0clk_vicap", "i0clk_vicap_io", 0,
950 GATE(I1CLK_VICAP, "i1clk_vicap", "i1clk_vicap_io", 0,
952 GATE(PCLK_VICAP, "pclk_vicap", "pclk_vicap_io", 0,
954 GATE(CLK_RXBYTECLKHS_0, "clk_rxbyteclkhs_0", "clk_rxbyteclkhs_0_io", 0,
956 GATE(CLK_RXBYTECLKHS_1, "clk_rxbyteclkhs_1", "clk_rxbyteclkhs_1_io", 0,
959 GATE(PCLK_VICAP_VEPU, "pclk_vicap_vepu", "pclk_vicap_vepu_io", 0,
961 GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
964 GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,