1 // SPDX-License-Identifier: GPL-2.0
4  * Author: Elaine Zhang <zhangqing@rock-chips.com>
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/rv1106-cru.h>
984 		pr_warn("CRU:\n");  in rv1106_dump_cru()
1000 	if ((rate0 - target_rate) < (target_rate >> 5))  in _cru_pvtpll_calibrate()
1012 	if (abs(rate1 - target_rate) < (target_rate >> 5))  in _cru_pvtpll_calibrate()
1015 	step = rate0 - rate1;  in _cru_pvtpll_calibrate()
1016 	delta = rate1 - target_rate;  in _cru_pvtpll_calibrate()
1023 	while (abs(rate0 - target_rate) >= (target_rate >> 5)) {  in _cru_pvtpll_calibrate()
1029 			length--;  in _cru_pvtpll_calibrate()
1043 	regmap_read(cru_ctx->grf, count_offset, &rate0);  in _grf_pvtpll_calibrate()
1047 	if ((rate0 - target_rate) < (target_rate >> 5))  in _grf_pvtpll_calibrate()
1050 	regmap_read(cru_ctx->grf, length_offset, &length_ori);  in _grf_pvtpll_calibrate()
1056 	regmap_write(cru_ctx->grf, length_offset, val);  in _grf_pvtpll_calibrate()
1058 	regmap_read(cru_ctx->grf, count_offset, &rate1);  in _grf_pvtpll_calibrate()
1061 	if (abs(rate1 - target_rate) < (target_rate >> 5))  in _grf_pvtpll_calibrate()
1064 	step = rate0 - rate1;  in _grf_pvtpll_calibrate()
1065 	delta = rate1 - target_rate;  in _grf_pvtpll_calibrate()
1068 	regmap_write(cru_ctx->grf, length_offset, val);  in _grf_pvtpll_calibrate()
1070 	regmap_read(cru_ctx->grf, count_offset, &rate0);  in _grf_pvtpll_calibrate()
1072 	while (abs(rate0 - target_rate) >= (target_rate >> 5)) {  in _grf_pvtpll_calibrate()
1078 			length--;  in _grf_pvtpll_calibrate()
1082 		regmap_write(cru_ctx->grf, length_offset, val);  in _grf_pvtpll_calibrate()
1084 		regmap_read(cru_ctx->grf, count_offset, &rate0);  in _grf_pvtpll_calibrate()
1119 	writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);  in rockchip_rv1106_pvtpll_init()
1121 	regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,  in rockchip_rv1106_pvtpll_init()
1123 	regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,  in rockchip_rv1106_pvtpll_init()
1125 	regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x3, PVTPLL_EN_MASK,  in rockchip_rv1106_pvtpll_init()
1128 	writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL0_CON0_H);  in rockchip_rv1106_pvtpll_init()
1129 	writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL0_CON1_L);  in rockchip_rv1106_pvtpll_init()
1130 	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL0_CON2_H);  in rockchip_rv1106_pvtpll_init()
1131 	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL0_CON0_L);  in rockchip_rv1106_pvtpll_init()
1133 	writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL1_CON0_H);  in rockchip_rv1106_pvtpll_init()
1134 	writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL1_CON1_L);  in rockchip_rv1106_pvtpll_init()
1135 	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);  in rockchip_rv1106_pvtpll_init()
1136 	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);  in rockchip_rv1106_pvtpll_init()
1160 		pr_err("%s: could not map cru region\n", __func__);  in rv1106_clk_init()
1176 	cru_clks = ctx->clk_data.clks;  in rv1106_clk_init()
1204 CLK_OF_DECLARE(rv1106_cru, "rockchip,rv1106-cru", rv1106_clk_init);
1213 		pr_err("%s: could not map cru grf region\n", __func__);  in rv1106_grf_clk_init()
1226 CLK_OF_DECLARE(rv1106_grf_cru, "rockchip,rv1106-grf-cru", rv1106_grf_clk_init);
1243 		.compatible = "rockchip,rv1106-cru",
1246 		.compatible = "rockchip,rv1106-grf-cru",
1255 	struct device_node *np = pdev->dev.of_node;  in clk_rv1106_probe()
1259 	match = of_match_device(clk_rv1106_match_table, &pdev->dev);  in clk_rv1106_probe()
1260 	if (!match || !match->data)  in clk_rv1106_probe()
1261 		return -EINVAL;  in clk_rv1106_probe()
1263 	init_data = match->data;  in clk_rv1106_probe()
1264 	if (init_data->inits)  in clk_rv1106_probe()
1265 		init_data->inits(np);  in clk_rv1106_probe()
1272 		.name	= "clk-rv1106",
1278 MODULE_DESCRIPTION("Rockchip RV1106 Clock Driver");