clk/rockchip/clk-rk3528.c

1 // SPDX-License-Identifier: GPL-2.0
4  * Author: Joseph Chen <chenjh@rock-chips.com>
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/rk3528-cru.h>
27  *   - frac mode: refdiv can be 1 or 2 only
28  *   - int mode:  refdiv has no special limit
29  *   - VCO range: [950, 3800] MHZ
32  *   - int mode:  refdiv can be 1 or 2 only
33  *   - VCO range: [475, 1900] MHZ
90 /* SIGN-OFF: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
253  * CRU Clock-Architecture
721 	/* vo */
1124 	clks = ctx->clk_data.clks;  in rk3528_clk_init()
1148 CLK_OF_DECLARE(rk3528_cru, "rockchip,rk3528-cru", rk3528_clk_init);
1157 		pr_err("%s: could not map cru grf region\n", __func__);  in rk3528_grf_clk_init()
1163 		pr_err("%s: rockchip grf clk init failed\n", __func__);  in rk3528_grf_clk_init()
1173 CLK_OF_DECLARE(rk3528_grf_cru, "rockchip,rk3528-grf-cru", rk3528_grf_clk_init);