Lines Matching full:gate
305 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
314 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
323 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
332 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
341 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
350 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
359 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
368 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
377 GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
386 GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
395 GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
404 GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
413 GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
420 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL,
426 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,
428 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
430 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
438 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0,
448 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0,
450 GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL,
452 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
454 GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0,
456 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
458 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
460 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
462 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
464 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0,
466 GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0,
468 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED,
478 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
480 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
482 GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
484 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
487 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
489 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
491 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
493 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
495 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
497 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
499 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
503 GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
505 GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
508 GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0,
510 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL,
513 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0,
515 GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0,
517 GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
519 GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL,
521 GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL,
523 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
525 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
527 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
529 GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0,
531 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
533 GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0,
535 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
542 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
554 GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0,
556 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
573 GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
575 GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL,
579 GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL,
581 GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL,
587 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED,
589 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
591 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
594 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
596 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL,
598 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
601 GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
603 GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
605 GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL,
607 GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL,
609 GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL,
619 GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0,
632 GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL,
634 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
641 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0,
648 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0,
654 GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL,
656 GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL,
658 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0,
660 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0,
662 GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0,
664 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0,
666 GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0,
668 GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0,
670 GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0,
672 GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0,
688 GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0,
690 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0,
692 GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0,
694 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0,
707 GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
709 GATE(CLK_UART_JTAG, "clk_uart_jtag", "xin24m", 0,
718 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
725 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
727 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0,
729 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0,
731 GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0,
733 GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0,
735 GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0,
737 GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0,
739 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0,
741 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
743 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0,
745 GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0,
751 GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0,
757 GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0,
759 GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0,
761 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
763 GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL,
765 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
767 GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0,
769 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0,
771 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0,
774 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0,
777 GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL,
779 GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL,
781 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0,
783 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0,
785 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0,
797 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0,
817 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
826 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
829 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
831 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
833 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
835 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
839 GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0,
844 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT,
848 GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0,
854 GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0,
856 GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0,
858 GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0,
861 GATE(CLK_USBHOST_OHCI, "clk_usbhost_ohci", "clk_usbhost_ohci_io", 0,
863 GATE(CLK_USBHOST_UTMI, "clk_usbhost_utmi", "clk_usbhost_utmi_io", 0,
865 GATE(CLK_HDMIPHY_TMDSSRC, "clk_hdmiphy_tmdssrc", "clk_hdmiphy_tmdssrc_io", 0,
867 GATE(CLK_HDMIPHY_PREP, "clk_hdmiphy_prep", "clk_hdmiphy_prep_io", 0,
871 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
873 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
875 GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
877 GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
879 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
881 GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
890 GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
892 GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL,
894 GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0,
896 GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0,
898 GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0,
900 GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0,
902 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0,
904 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0,
906 GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0,
908 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0,
910 GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0,
912 GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
914 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0,
916 GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0,
918 GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0,
920 GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL,
922 GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
924 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0,
926 GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0,
928 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0,
930 GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL,
932 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0,
951 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0,
953 GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0,
955 GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0,
957 GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0,
959 GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0,
962 GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0,
964 GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0,
966 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0,
968 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0,
995 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
1031 GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0,
1034 GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
1038 GATE(CLK_PIPE_USB3OTG_COMBO, "clk_pipe_usb3otg_combo", "clk_pipe_usb3otg_io", 0,
1040 GATE(CLK_UTMI_USB3OTG, "clk_utmi_usb3otg", "clk_utmi_usb3otg_io", 0,
1042 GATE(CLK_PCIE_PIPE_PHY, "clk_pcie_pipe_phy", "clk_pipe_usb3otg_io", 0,
1063 GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0,
1065 GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0,
1067 GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "clk_gmac0_io_i", 0,
1069 GATE(CLK_SCRKEYGEN, "clk_scrkeygen", "clk_pmupvtm_out", 0,
1071 GATE(CLK_PVTM_OSCCHK, "clk_pvtm_oscchk", "clk_pmupvtm_out", 0,