Lines Matching full:gate
282 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
284 GATE(0, "cpll_core", "cpll", CLK_IGNORE_UNUSED,
286 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
295 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
298 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
312 GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IS_CRITICAL,
314 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL,
316 GATE(0, "aclk_core2gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
318 GATE(0, "aclk_gic2core", "aclk_gic_pre", CLK_IGNORE_UNUSED,
320 GATE(0, "aclk_spinlock", "aclk_gic_pre", CLK_IGNORE_UNUSED,
329 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
331 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
333 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
335 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED,
348 GATE(SCLK_NPU, "clk_npu", "clk_npu_pre", 0,
357 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
359 GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IS_CRITICAL,
364 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
366 GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IS_CRITICAL,
369 GATE(SCLK_PVTM_NPU, "clk_pvtm_npu", "xin24m", 0,
375 GATE(ACLK_IMEM0, "aclk_imem0", "aclk_imem_pre", CLK_IGNORE_UNUSED,
377 GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
379 GATE(ACLK_IMEM1, "aclk_imem1", "aclk_imem_pre", CLK_IGNORE_UNUSED,
381 GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
383 GATE(ACLK_IMEM2, "aclk_imem2", "aclk_imem_pre", CLK_IGNORE_UNUSED,
385 GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
387 GATE(ACLK_IMEM3, "aclk_imem3", "aclk_imem_pre", CLK_IGNORE_UNUSED,
389 GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
399 GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
402 GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
404 GATE(0, "aclk_split", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
406 GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
408 GATE(0, "clk_ddrdfi_ctl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
410 GATE(0, "clk_stdby", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
412 GATE(0, "aclk_ddrc", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
414 GATE(0, "clk_core_ddrc", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
417 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
419 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
429 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
431 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
433 GATE(PCLK_MSCH, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
435 GATE(PCLK_STDBY, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
437 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
439 GATE(0, "pclk_ddrdfi_ctl", "pclk_ddr", CLK_IGNORE_UNUSED,
452 GATE(0, "hsclk_vio_niu", "hsclk_vio", CLK_IGNORE_UNUSED,
454 GATE(0, "lsclk_vio_niu", "lsclk_vio", CLK_IGNORE_UNUSED,
456 GATE(ACLK_VOPRAW, "aclk_vopraw", "hsclk_vio", 0,
458 GATE(HCLK_VOPRAW, "hclk_vopraw", "lsclk_vio", 0,
460 GATE(ACLK_VOPLITE, "aclk_voplite", "hsclk_vio", 0,
462 GATE(HCLK_VOPLITE, "hclk_voplite", "lsclk_vio", 0,
464 GATE(PCLK_DSI_TX, "pclk_dsi_tx", "lsclk_vio", 0,
466 GATE(PCLK_CSI_TX, "pclk_csi_tx", "lsclk_vio", 0,
468 GATE(ACLK_RGA, "aclk_rga", "hsclk_vio", 0,
470 GATE(HCLK_RGA, "hclk_rga", "lsclk_vio", 0,
472 GATE(ACLK_ISP, "aclk_isp", "hsclk_vio", 0,
474 GATE(HCLK_ISP, "hclk_isp", "lsclk_vio", 0,
476 GATE(ACLK_CIF, "aclk_cif", "hsclk_vio", 0,
478 GATE(HCLK_CIF, "hclk_cif", "lsclk_vio", 0,
480 GATE(PCLK_CSI2HOST, "pclk_csi2host", "lsclk_vio", 0,
490 GATE(DCLK_VOPRAW, "dclk_vopraw", "dclk_vopraw_mux", 0,
500 GATE(DCLK_VOPLITE, "dclk_voplite", "dclk_voplite_mux", 0,
535 GATE(0, "hsclk_pcie_niu", "hsclk_pcie", CLK_IGNORE_UNUSED,
537 GATE(0, "lsclk_pcie_niu", "lsclk_pcie", CLK_IGNORE_UNUSED,
539 GATE(0, "pclk_pcie_grf", "lsclk_pcie", CLK_IGNORE_UNUSED,
541 GATE(ACLK_USB3OTG, "aclk_usb3otg", "hsclk_pcie", 0,
543 GATE(HCLK_HOST, "hclk_host", "lsclk_pcie", 0,
545 GATE(HCLK_HOST_ARB, "hclk_host_arb", "lsclk_pcie", CLK_IGNORE_UNUSED,
553 GATE(0, "aclk_pcie_niu", "aclk_pcie", CLK_IGNORE_UNUSED,
555 GATE(ACLK_PCIE_MST, "aclk_pcie_mst", "aclk_pcie", CLK_IGNORE_UNUSED,
557 GATE(ACLK_PCIE_SLV, "aclk_pcie_slv", "aclk_pcie", CLK_IGNORE_UNUSED,
559 GATE(0, "pclk_pcie_niu", "pclk_pcie_pre", CLK_IGNORE_UNUSED,
561 GATE(0, "pclk_pcie_dbi", "pclk_pcie_pre", CLK_IGNORE_UNUSED,
563 GATE(PCLK_PCIE, "pclk_pcie", "pclk_pcie_pre", 0,
573 GATE(SCLK_USB3_OTG0_REF, "clk_usb3_otg0_ref", "xin24m", 0,
595 GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IS_CRITICAL,
597 GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IS_CRITICAL,
602 GATE(0, "hclk_mmc_sfc", "msclk_peri", CLK_IGNORE_UNUSED,
604 GATE(0, "hclk_mmc_sfc_niu", "hclk_mmc_sfc", CLK_IGNORE_UNUSED,
606 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_sfc", 0,
608 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_sfc", 0,
660 GATE(0, "pclk_sd_gmac", "lsclk_peri", CLK_IGNORE_UNUSED,
662 GATE(0, "aclk_sd_gmac", "msclk_peri", CLK_IGNORE_UNUSED,
664 GATE(0, "hclk_sd_gmac", "msclk_peri", CLK_IGNORE_UNUSED,
666 GATE(0, "pclk_gmac_niu", "pclk_sd_gmac", CLK_IGNORE_UNUSED,
668 GATE(PCLK_GMAC, "pclk_gmac", "pclk_sd_gmac", 0,
670 GATE(0, "aclk_gmac_niu", "aclk_sd_gmac", CLK_IGNORE_UNUSED,
672 GATE(ACLK_GMAC, "aclk_gmac", "aclk_sd_gmac", 0,
674 GATE(0, "hclk_gmac_niu", "hclk_sd_gmac", CLK_IGNORE_UNUSED,
676 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sd_gmac", 0,
678 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd_gmac", 0,
690 GATE(SCLK_GMAC_REF, "clk_gmac_ref", "clk_gmac", 0,
692 GATE(0, "clk_gmac_tx_src", "clk_gmac", 0,
694 GATE(0, "clk_gmac_rx_src", "clk_gmac", 0,
696 GATE(SCLK_GMAC_REFOUT, "clk_gmac_refout", "clk_gmac", 0,
727 GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IS_CRITICAL,
729 GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IS_CRITICAL,
731 GATE(0, "msclk_sub", "msclk_bus_pre", CLK_IGNORE_UNUSED,
733 GATE(ACLK_DMAC, "aclk_dmac", "msclk_bus_pre", CLK_IGNORE_UNUSED,
735 GATE(HCLK_ROM, "hclk_rom", "msclk_bus_pre", CLK_IGNORE_UNUSED,
737 GATE(ACLK_CRYPTO, "aclk_crypto", "msclk_bus_pre", 0,
739 GATE(HCLK_CRYPTO, "hclk_crypto", "msclk_bus_pre", 0,
741 GATE(ACLK_DCF, "aclk_dcf", "msclk_bus_pre", 0,
743 GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IS_CRITICAL,
745 GATE(PCLK_DCF, "pclk_dcf", "lsclk_bus_pre", 0,
747 GATE(PCLK_UART1, "pclk_uart1", "lsclk_bus_pre", 0,
749 GATE(PCLK_UART2, "pclk_uart2", "lsclk_bus_pre", 0,
751 GATE(PCLK_UART3, "pclk_uart3", "lsclk_bus_pre", 0,
753 GATE(PCLK_UART4, "pclk_uart4", "lsclk_bus_pre", 0,
755 GATE(PCLK_UART5, "pclk_uart5", "lsclk_bus_pre", 0,
757 GATE(PCLK_UART6, "pclk_uart6", "lsclk_bus_pre", 0,
759 GATE(PCLK_UART7, "pclk_uart7", "lsclk_bus_pre", 0,
761 GATE(PCLK_I2C1, "pclk_i2c1", "lsclk_bus_pre", 0,
763 GATE(PCLK_I2C2, "pclk_i2c2", "lsclk_bus_pre", 0,
765 GATE(PCLK_I2C3, "pclk_i2c3", "lsclk_bus_pre", 0,
767 GATE(PCLK_I2C4, "pclk_i2c4", "lsclk_bus_pre", 0,
769 GATE(PCLK_I2C5, "pclk_i2c5", "lsclk_bus_pre", 0,
771 GATE(PCLK_SPI0, "pclk_spi0", "lsclk_bus_pre", 0,
773 GATE(PCLK_SPI1, "pclk_spi1", "lsclk_bus_pre", 0,
775 GATE(PCLK_SPI2, "pclk_spi2", "lsclk_bus_pre", 0,
777 GATE(PCLK_TSADC, "pclk_tsadc", "lsclk_bus_pre", 0,
779 GATE(PCLK_SARADC, "pclk_saradc", "lsclk_bus_pre", 0,
781 GATE(PCLK_EFUSE, "pclk_efuse", "lsclk_bus_pre", 0,
783 GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_bus_pre", 0,
785 GATE(PCLK_GPIO2, "pclk_gpio2", "lsclk_bus_pre", 0,
787 GATE(PCLK_GPIO3, "pclk_gpio3", "lsclk_bus_pre", 0,
789 GATE(PCLK_GPIO4, "pclk_gpio4", "lsclk_bus_pre", 0,
791 GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_bus_pre", 0,
793 GATE(PCLK_PWM1, "pclk_pwm1", "lsclk_bus_pre", 0,
795 GATE(PCLK_PWM2, "pclk_pwm2", "lsclk_bus_pre", 0,
797 GATE(PCLK_TIMER, "pclk_timer", "lsclk_bus_pre", 0,
799 GATE(PCLK_WDT, "pclk_wdt", "lsclk_bus_pre", 0,
801 GATE(0, "pclk_grf", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
803 GATE(0, "pclk_sgrf", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
805 GATE(0, "hclk_audio_pre", "msclk_bus_pre", 0,
807 GATE(0, "pclk_top_pre", "lsclk_bus_pre", CLK_IS_CRITICAL,
827 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
840 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0,
853 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
866 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
879 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", 0,
892 GATE(SCLK_UART6, "clk_uart6", "clk_uart6_mux", 0,
905 GATE(SCLK_UART7, "clk_uart7", "clk_uart7_mux", 0,
971 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
973 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
975 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
977 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
979 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
981 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
990 GATE(0, "hclk_audio_niu", "hclk_audio_pre", CLK_IGNORE_UNUSED,
992 GATE(HCLK_VAD, "hclk_vad", "hclk_audio_pre", 0,
994 GATE(HCLK_PDM, "hclk_pdm", "hclk_audio_pre", 0,
996 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_pre", 0,
998 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio_pre", 0,
1008 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
1046 GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
1058 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 0, GFLAGS),
1059 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 1, GFLAGS),
1060 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 2, GFLAGS),
1061 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, RK1808_CLKGATE_CON(19), 3, GFLAGS),
1062 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, RK1808_CLKGATE_CON(19), 4, GFLAGS),
1064 …GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON…
1065 GATE(0, "pclk_usb3_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 7, GFLAGS),
1066 GATE(0, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 8, GFLAGS),
1100 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
1103 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
1136 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
1137 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 2, GFLAGS),
1138 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 3, GFLAGS),
1139 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 4, GFLAGS),
1140 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 5, GFLAGS),
1141 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 6, GFLAGS),
1142 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 7, GFLAGS),
1143 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 8, GFLAGS),
1144 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 9, GFLAGS),