clk/rockchip/clk-rk1808.c

309 	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
323 	COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_p, 0,
351 	COMPOSITE(0, "aclk_npu_pre", mux_gpll_cpll_p, 0,
354 	COMPOSITE(0, "hclk_npu_pre", mux_gpll_cpll_p, 0,
372 	COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
392 	COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
446 	COMPOSITE(HSCLK_VIO, "hsclk_vio", mux_gpll_cpll_p, 0,
483 	COMPOSITE(0, "dclk_vopraw_src", mux_cpll_gpll_npll_p, 0,
493 	COMPOSITE(0, "dclk_voplite_src", mux_cpll_gpll_npll_p, 0,
507 	COMPOSITE(SCLK_RGA, "clk_rga", mux_gpll_cpll_npll_p, 0,
511 	COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
515 	COMPOSITE(DCLK_CIF, "dclk_cif", mux_cpll_gpll_npll_p, 0,
519 	COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_24m_npll_gpll_usb480m_p, 0,
548 	COMPOSITE(ACLK_PCIE, "aclk_pcie", mux_gpll_cpll_p, 0,
566 	COMPOSITE(0, "clk_pcie_aux_src", mux_cpll_gpll_npll_p, 0,
576 	COMPOSITE(SCLK_USB3_OTG0_SUSPEND, "clk_usb3_otg0_suspend", mux_usb3_otg0_suspend_p, 0,
611 	COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
626 	COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div",
640 	COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
654 	COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
681 	COMPOSITE(SCLK_GMAC_OUT, "clk_gmac_out", mux_cpll_npll_ppll_p, 0,
685 	COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_cpll_npll_ppll_p, 0,
810 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0,
813 	COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_p, 0,
817 	COMPOSITE(0, "clk_uart1_src", mux_gpll_usb480m_cpll_npll_p, 0,
830 	COMPOSITE(0, "clk_uart2_src", mux_gpll_usb480m_cpll_npll_p, 0,
843 	COMPOSITE(0, "clk_uart3_src", mux_gpll_usb480m_cpll_npll_p, 0,
856 	COMPOSITE(0, "clk_uart4_src", mux_gpll_usb480m_cpll_npll_p, 0,
869 	COMPOSITE(0, "clk_uart5_src", mux_gpll_usb480m_cpll_npll_p, 0,
882 	COMPOSITE(0, "clk_uart6_src", mux_gpll_usb480m_cpll_npll_p, 0,
895 	COMPOSITE(0, "clk_uart7_src", mux_gpll_usb480m_cpll_npll_p, 0,
908 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
911 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
914 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
917 	COMPOSITE(SCLK_I2C4, "clk_i2c4", mux_gpll_xin24m_p, 0,
920 	COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_gpll_xin24m_p, 0,
924 	COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
927 	COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
930 	COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0,
941 	COMPOSITE(SCLK_EFUSE_S, "clk_efuse_s", mux_gpll_cpll_xin24m_p, 0,
944 	COMPOSITE(SCLK_EFUSE_NS, "clk_efuse_ns", mux_gpll_cpll_xin24m_p, 0,
948 	COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
951 	COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
954 	COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
957 	COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
961 	COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
964 	COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
967 	COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_gpll_xin24m_p, 0,
1001 	COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_cpll_npll_p, 0,
1011 	COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_npll_p, 0,
1025 	COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_npll_p, 0,
1039 	COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_gpll_cpll_npll_p, 0,
1090 	COMPOSITE(0, "clk_uart0_pmu_src", mux_gpll_usb480m_cpll_ppll_p, 0,
1106 	COMPOSITE(SCLK_PMU_I2C0, "clk_pmu_i2c0", mux_ppll_xin24m_p, 0,
1110 	COMPOSITE(DBCLK_PMU_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,