Lines Matching full:pmucru
828 clocks = <&pmucru XIN_OSC0_EDPPHY_G>;
854 pmucru: clock-controller@fdd00000 { label
855 compatible = "rockchip,rk3568-pmucru";
862 assigned-clocks = <&pmucru SCLK_32K_IOE>;
863 assigned-clock-parents = <&pmucru CLK_RTC_32K>;
874 <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
875 <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
876 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
914 <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
921 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
935 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
951 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
962 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
973 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
986 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
2068 <&pmucru PLL_HPLL>,
2107 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
3468 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
3471 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
3484 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
3487 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
3500 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
3503 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
3517 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
3533 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
3586 clocks = <&pmucru CLK_USBPHY0_REF>;
3610 clocks = <&pmucru CLK_USBPHY1_REF>;
3631 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
3652 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;