Lines Matching full:cru
6 #include <dt-bindings/clock/rk3568-cru.h>
518 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
519 <&cru CLK_SATA0_RXOOB>;
533 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
534 <&cru CLK_SATA1_RXOOB>;
548 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
549 <&cru CLK_SATA2_RXOOB>;
562 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
563 <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
580 resets = <&cru SRST_USB3OTG0>;
598 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
599 <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
616 resets = <&cru SRST_USB3OTG1>;
652 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
653 <&cru PCLK_USB>, <&usb2phy1>;
664 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
665 <&cru PCLK_USB>, <&usb2phy1>;
676 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
677 <&cru PCLK_USB>, <&usb2phy1>;
688 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
689 <&cru PCLK_USB>, <&usb2phy1>;
824 clocks = <&cru PCLK_EDPPHY_GRF>;
866 cru: clock-controller@fdd20000 { label
867 compatible = "rockchip,rk3568-cru";
874 <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
875 <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
876 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
877 <&cru CPLL_500M>, <&cru CPLL_333M>,
878 <&cru CPLL_250M>, <&cru CPLL_125M>,
879 <&cru CPLL_100M>, <&cru CPLL_62P5M>,
880 <&cru CPLL_50M>, <&cru CPLL_25M>,
881 <&cru PLL_GPLL>,
882 <&cru ACLK_BUS>, <&cru PCLK_BUS>,
883 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
884 <&cru HCLK_TOP>, <&cru PCLK_TOP>,
885 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
886 <&cru PLL_NPLL>, <&cru ACLK_PIPE>,
887 <&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>,
888 <&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>,
889 <&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>,
890 <&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>,
891 <&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>,
892 <&cru ACLK_VOP>;
914 <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
915 <&cru PLL_GPLL>;
1005 clocks = <&cru ACLK_NPU_PRE>,
1006 <&cru HCLK_NPU_PRE>,
1007 <&cru PCLK_NPU_PRE>;
1013 clocks = <&cru ACLK_GPU_PRE>,
1014 <&cru PCLK_GPU_PRE>;
1020 clocks = <&cru HCLK_VI>,
1021 <&cru PCLK_VI>;
1028 clocks = <&cru HCLK_VO>,
1029 <&cru PCLK_VO>,
1030 <&cru ACLK_VOP_PRE>;
1037 clocks = <&cru HCLK_RGA_PRE>,
1038 <&cru PCLK_RGA_PRE>;
1048 clocks = <&cru HCLK_VPU_PRE>;
1052 clocks = <&cru HCLK_RKVDEC_PRE>;
1058 clocks = <&cru HCLK_RKVENC_PRE>;
1065 clocks = <&cru PCLK_PIPE>;
1085 clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>;
1087 resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>;
1097 clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
1099 assigned-clocks = <&cru CLK_NPU>;
1101 resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>;
1228 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>;
1247 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
1331 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
1333 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
1346 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>,
1347 <&cru HCLK_NPU_PRE>;
1349 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
1360 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1362 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
1378 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1388 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
1398 clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
1411 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1414 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
1430 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1440 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
1443 resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
1459 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
1469 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
1471 resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>,
1472 <&cru SRST_IEP_CORE>;
1487 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1499 clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
1509 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
1510 <&cru CLK_RKVENC_CORE>;
1513 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
1514 <&cru SRST_RKVENC_CORE>;
1516 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1562 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
1577 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
1578 <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
1579 <&cru CLK_RKVDEC_HEVC_CA>;
1587 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
1588 <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
1589 <&cru SRST_RKVDEC_HEVC_CA>;
1590 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
1591 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
1642 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1656 clocks = <&cru PCLK_CSI2HOST1>;
1658 resets = <&cru SRST_P_CSI2HOST1>;
1670 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
1671 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
1674 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
1675 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
1676 <&cru SRST_I_VICAP>;
1680 assigned-clocks = <&cru DCLK_VICAP>;
1693 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
1732 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
1734 resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>;
1748 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1782 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
1783 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
1784 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
1785 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
1786 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
1792 resets = <&cru SRST_A_GMAC0>;
1833 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
1834 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
1835 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
1836 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
1837 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
1843 resets = <&cru SRST_A_GMAC1>;
1883 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
1974 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1985 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
1987 resets = <&cru SRST_P_DSITX_0>;
2025 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
2027 resets = <&cru SRST_P_DSITX_1>;
2065 clocks = <&cru PCLK_HDMI_HOST>,
2066 <&cru CLK_HDMI_SFR>,
2067 <&cru CLK_HDMI_CEC>,
2069 <&cru HCLK_VOP>;
2107 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
2108 <&cru CLK_EDP_200M>, <&cru HCLK_VO>;
2110 resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>;
2307 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
2308 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
2311 resets = <&cru SRST_SDMMC2>;
2416 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
2417 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
2418 <&cru CLK_PCIE20_AUX_NDFT>;
2451 resets = <&cru SRST_PCIE20_POWERUP>;
2469 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
2470 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
2471 <&cru CLK_PCIE30X1_AUX_NDFT>;
2504 resets = <&cru SRST_PCIE30X1_POWERUP>;
2523 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
2524 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
2525 <&cru CLK_PCIE30X2_AUX_NDFT>;
2558 resets = <&cru SRST_PCIE30X2_POWERUP>;
2585 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
2586 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
2589 resets = <&cru SRST_SDMMC0>;
2600 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
2601 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
2604 resets = <&cru SRST_SDMMC1>;
2613 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
2615 assigned-clocks = <&cru SCLK_SFC>;
2626 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
2627 <&cru CCLK_EMMC>;
2629 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
2630 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
2631 <&cru TCLK_EMMC>;
2633 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
2634 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
2635 <&cru SRST_T_EMMC>;
2645 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
2654 clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
2655 <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>;
2657 assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>;
2659 resets = <&cru SRST_CRYPTO_NS_CORE>;
2667 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
2669 resets = <&cru SRST_TRNG_NS>;
2679 clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
2680 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
2682 resets = <&cru SRST_OTPPHY>;
2754 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
2758 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
2760 rockchip,cru = <&cru>;
2771 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
2775 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
2777 rockchip,cru = <&cru>;
2800 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
2804 rockchip,cru = <&cru>;
2820 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
2824 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
2826 rockchip,cru = <&cru>;
2841 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
2860 clocks = <&cru HCLK_VAD>;
2877 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
2887 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
2900 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
2901 <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>;
2905 resets = <&cru SRST_ACDCDIG>;
2917 clocks = <&cru ACLK_BUS>;
2928 clocks = <&cru ACLK_BUS>;
2940 clocks = <&cru PCLK_SCR>;
2949 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; // by manic
2951 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
2963 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
2965 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
2977 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
2979 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
2990 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
3003 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
3016 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
3029 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
3042 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
3056 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
3063 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
3075 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
3092 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
3109 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
3126 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
3141 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
3155 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
3169 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
3183 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
3197 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
3211 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
3225 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
3239 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
3253 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
3269 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
3280 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
3291 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
3304 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
3315 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
3326 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
3337 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
3350 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
3361 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
3372 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
3383 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
3396 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
3406 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
3408 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
3410 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
3411 <&cru SRST_TSADCPHY>;
3417 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
3443 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
3445 resets = <&cru SRST_P_SARADC>;
3458 clocks = <&cru PCLK_MAILBOX>;
3468 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
3469 <&cru PCLK_PIPE>;
3473 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
3484 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
3485 <&cru PCLK_PIPE>;
3489 resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
3500 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
3501 <&cru PCLK_PIPE>;
3505 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
3518 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
3521 resets = <&cru SRST_P_MIPIDSIPHY0>;
3534 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
3537 resets = <&cru SRST_P_MIPIDSIPHY1>;
3547 clocks = <&cru PCLK_MIPICSIPHY>;
3589 assigned-clocks = <&cru USB480M>;
3632 <&cru PCLK_PCIE30PHY>;
3634 resets = <&cru SRST_PCIE30PHY>;
3664 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
3676 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
3688 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
3700 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;