Lines Matching +full:0 +full:xfe330000
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
73 clocks = <&scmi_clk 0>;
83 reg = <0x0 0x100>;
85 clocks = <&scmi_clk 0>;
93 reg = <0x0 0x200>;
95 clocks = <&scmi_clk 0>;
103 reg = <0x0 0x300>;
105 clocks = <&scmi_clk 0>;
115 arm,psci-suspend-param = <0x0010000>;
132 0 84000 0
139 rockchip,pvtm-ch = <0 5>;
147 rockchip,low-temp = <0>;
150 0 1992 75000
294 arm,smc-id = <0x82000010>;
296 #size-cells = <0>;
299 reg = <0x14>;
337 reg = <0x0 0x0 0x0 0x0>;
342 reg = <0x0 0x0 0x0 0x0>;
351 (0
362 (0
380 thermal-sensors = <&tsadc 0>;
382 threshold: trip-point-0 {
435 #clock-cells = <0>;
442 #clock-cells = <0>;
449 #clock-cells = <0>;
456 #clock-cells = <0>;
461 #clock-cells = <0>;
468 #clock-cells = <0>;
475 #clock-cells = <0>;
482 #clock-cells = <0>;
489 #clock-cells = <0>;
496 #clock-cells = <0>;
505 #clock-cells = <0>;
507 pinctrl-0 = <&clk32k_out0>;
512 reg = <0x0 0x0010f000 0x0 0x100>;
517 reg = <0 0xfc000000 0 0x1000>;
525 ports-implemented = <0x1>;
532 reg = <0 0xfc400000 0 0x1000>;
540 ports-implemented = <0x1>;
547 reg = <0 0xfc800000 0 0x1000>;
555 ports-implemented = <0x1>;
573 reg = <0x0 0xfcc00000 0x0 0x400000>;
609 reg = <0x0 0xfd000000 0x0 0x400000>;
637 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
638 <0x0 0xfd460000 0 0xc0000>; /* GICR */
644 reg = <0x0 0xfd440000 0x0 0x20000>;
650 reg = <0x0 0xfd800000 0x0 0x40000>;
662 reg = <0x0 0xfd840000 0x0 0x40000>;
674 reg = <0x0 0xfd880000 0x0 0x40000>;
686 reg = <0x0 0xfd8c0000 0x0 0x40000>;
698 reg = <0x0 0xfda00000 0x0 0x200000>;
704 reg = <0x0 0xfdc20000 0x0 0x10000>;
713 offset = <0x200>;
728 reg = <0x0 0xfdc50000 0x0 0x1000>;
733 reg = <0x0 0xfdc60000 0x0 0x10000>;
748 #size-cells = <0>;
750 port@0 {
751 reg = <0>;
753 #size-cells = <0>;
773 pinctrl-0 = <&lcdc_ctl>;
778 #size-cells = <0>;
780 port@0 {
781 reg = <0>;
783 #size-cells = <0>;
798 reg = <0x0 0xfdc70000 0x0 0x1000>;
803 reg = <0x0 0xfdc80000 0x0 0x1000>;
808 reg = <0x0 0xfdc90000 0x0 0x1000>;
813 reg = <0x0 0xfdca0000 0x0 0x8000>;
818 reg = <0x0 0xfdca8000 0x0 0x8000>;
823 reg = <0x0 0xfdcb0000 0x0 0x100>;
830 #phy-cells = <0>;
837 reg = <0x0 0xfdcb8000 0x0 0x10000>;
842 reg = <0x0 0xfdcc0000 0x0 0xb000>;
846 ranges = <0x0 0x0 0xfdcc0000 0xb000>;
849 rkvdec_sram: rkvdec-sram@0 {
850 reg = <0x0 0xb000>;
856 reg = <0x0 0xfdd00000 0x0 0x1000>;
868 reg = <0x0 0xfdd20000 0x0 0x1000>;
920 reg = <0x0 0xfdd40000 0x0 0x1000>;
925 pinctrl-0 = <&i2c0_xfer>;
927 #size-cells = <0>;
933 reg = <0x0 0xfdd50000 0x0 0x100>;
939 dmas = <&dmac0 0>, <&dmac0 1>;
941 pinctrl-0 = <&uart0_xfer>;
947 reg = <0x0 0xfdd70000 0x0 0x10>;
950 pinctrl-0 = <&pwm0m0_pins>;
958 reg = <0x0 0xfdd70010 0x0 0x10>;
961 pinctrl-0 = <&pwm1m0_pins>;
969 reg = <0x0 0xfdd70020 0x0 0x10>;
972 pinctrl-0 = <&pwm2m0_pins>;
980 reg = <0x0 0xfdd70030 0x0 0x10>;
985 pinctrl-0 = <&pwm3_pins>;
993 reg = <0x0 0xfdd90000 0x0 0x1000>;
999 #size-cells = <0>;
1080 reg = <0x0 0xfde00000 0x0 0x100>;
1082 #size-cells = <0>;
1083 pvtm@0 {
1084 reg = <0>;
1095 reg = <0x0 0xfde40000 0x0 0x10000>;
1117 rockchip,low-temp = <0>;
1120 0 1000 50000
1123 0 84000 0
1128 rockchip,pvtm-ch = <0 5>;
1197 0 84000 0
1201 rockchip,pvtm-ch = <0 5>;
1225 reg = <0x0 0xfde4b000 0x0 0x40>;
1231 #iommu-cells = <0>;
1237 reg = <0x0 0xfde60000 0x0 0x4000>;
1257 ls = <(-24002) 22823 0>;
1273 rockchip,low-temp = <0>;
1276 0 800 50000
1279 0 84000 0
1284 rockchip,pvtm-ch = <0 5>;
1326 reg = <0x0 0xfde80000 0x0 0x100>;
1328 #size-cells = <0>;
1341 reg = <0x0 0xfde90000 0x0 0x100>;
1343 #size-cells = <0>;
1357 reg = <0x0 0xfdea0400 0x0 0x400>;
1367 rockchip,taskqueue-node = <0>;
1368 rockchip,resetgroup-node = <0>;
1374 reg = <0x0 0xfdea0800 0x0 0x40>;
1380 #iommu-cells = <0>;
1386 reg = <0x0 0xfdeb0000 0x0 0x1000>;
1396 reg = <0x0 0xfdec0000 0x0 0x5000>;
1403 pinctrl-0 = <&ebc_pins>;
1409 reg = <0x0 0xfded0000 0x0 0x400>;
1426 reg = <0x0 0xfded0480 0x0 0x40>;
1432 #iommu-cells = <0>;
1438 reg = <0x0 0xfdee0000 0x0 0x400>;
1455 reg = <0x0 0xfdee0800 0x0 0x40>;
1461 #iommu-cells = <0>;
1467 reg = <0x0 0xfdef0000 0x0 0x500>;
1484 reg = <0x0 0xfdef0800 0x0 0x100>;
1489 #iommu-cells = <0>;
1497 reg = <0x0 0xfdf00000 0x0 0x74>;
1506 reg = <0x0 0xfdf40000 0x0 0x400>;
1512 rockchip,normal-rates = <297000000>, <0>, <297000000>;
1534 0 84000 0
1538 rockchip,pvtm-ch = <0 5>;
1558 reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
1566 #iommu-cells = <0>;
1573 reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>;
1582 rockchip,normal-rates = <297000000>, <0>, <297000000>,
1584 rockchip,advanced-rates = <396000000>, <0>, <396000000>,
1604 rockchip,rcb-iova = <0x10000000 65536>;
1616 1 80 0
1620 0 84000 0
1623 rockchip,pvtm-ch = <0 5>;
1639 reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
1645 #iommu-cells = <0>;
1651 reg = <0x0 0xfdfb0000 0x0 0x10000>;
1665 reg = <0x0 0xfdfe0000 0x0 0x8000>;
1690 reg = <0x0 0xfdfe0800 0x0 0x100>;
1697 #iommu-cells = <0>;
1727 reg = <0x0 0xfdff0000 0x0 0x10000>;
1739 rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
1745 reg = <0x0 0xfdff1a00 0x0 0x100>;
1751 #iommu-cells = <0>;
1770 reg = <0x0 0xfe010000 0x0 0x10000>;
1777 reg = <0x0 0xfe2a0000 0x0 0x10000>;
1805 #address-cells = <0x1>;
1806 #size-cells = <0x0>;
1812 snps,blen = <0 0 0 0 16 8 4>;
1828 reg = <0x0 0xfe010000 0x0 0x10000>;
1856 #address-cells = <0x1>;
1857 #size-cells = <0x0>;
1863 snps,blen = <0 0 0 0 16 8 4>;
1879 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
1891 #size-cells = <0>;
1893 vp0: port@0 {
1895 #size-cells = <0>;
1896 reg = <0>;
1898 vp0_out_dsi0: endpoint@0 {
1899 reg = <0>;
1921 #size-cells = <0>;
1924 vp1_out_dsi0: endpoint@0 {
1925 reg = <0>;
1952 #size-cells = <0>;
1956 vp2_out_lvds: endpoint@0 {
1957 reg = <0>;
1971 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
1976 #iommu-cells = <0>;
1983 reg = <0x0 0xfe060000 0x0 0x10000>;
1994 #size-cells = <0>;
1999 #size-cells = <0>;
2001 dsi0_in: port@0 {
2002 reg = <0>;
2004 #size-cells = <0>;
2006 dsi0_in_vp0: endpoint@0 {
2007 reg = <0>;
2023 reg = <0x0 0xfe070000 0x0 0x10000>;
2034 #size-cells = <0>;
2039 #size-cells = <0>;
2041 dsi1_in: port@0 {
2042 reg = <0>;
2044 #size-cells = <0>;
2046 dsi1_in_vp0: endpoint@0 {
2047 reg = <0>;
2063 reg = <0x0 0xfe0a0000 0x0 0x20000>;
2074 #sound-dai-cells = <0>;
2076 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
2081 #size-cells = <0>;
2083 port@0 {
2084 reg = <0>;
2086 #size-cells = <0>;
2088 hdmi_in_vp0: endpoint@0 {
2089 reg = <0>;
2105 reg = <0x0 0xfe0c0000 0x0 0x10000>;
2119 #size-cells = <0>;
2121 edp_in: port@0 {
2122 reg = <0>;
2124 #size-cells = <0>;
2126 edp_in_vp0: endpoint@0 {
2127 reg = <0>;
2143 reg = <0x0 0xfe102000 0x0 0x400>;
2148 reg = <0x0 0xfe102400 0x0 0x400>;
2153 reg = <0x0 0xfe102800 0x0 0x400>;
2158 reg = <0x0 0xfe102c00 0x0 0x400>;
2163 reg = <0x0 0xfe103000 0x0 0x400>;
2168 reg = <0x0 0xfe128000 0x0 0x20>;
2173 reg = <0x0 0xfe138080 0x0 0x20>;
2178 reg = <0x0 0xfe138100 0x0 0x20>;
2183 reg = <0x0 0xfe138180 0x0 0x20>;
2188 reg = <0x0 0xfe148000 0x0 0x20>;
2193 reg = <0x0 0xfe148080 0x0 0x20>;
2198 reg = <0x0 0xfe148100 0x0 0x20>;
2203 reg = <0x0 0xfe150000 0x0 0x20>;
2208 reg = <0x0 0xfe158000 0x0 0x20>;
2213 reg = <0x0 0xfe158100 0x0 0x20>;
2218 reg = <0x0 0xfe158180 0x0 0x20>;
2223 reg = <0x0 0xfe158200 0x0 0x20>;
2228 reg = <0x0 0xfe158280 0x0 0x20>;
2233 reg = <0x0 0xfe158300 0x0 0x20>;
2238 reg = <0x0 0xfe180000 0x0 0x20>;
2243 reg = <0x0 0xfe190000 0x0 0x20>;
2248 reg = <0x0 0xfe190080 0x0 0x20>;
2253 reg = <0x0 0xfe190100 0x0 0x20>;
2258 reg = <0x0 0xfe190200 0x0 0x20>;
2263 reg = <0x0 0xfe190280 0x0 0x20>;
2268 reg = <0x0 0xfe190300 0x0 0x20>;
2273 reg = <0x0 0xfe190380 0x0 0x20>;
2278 reg = <0x0 0xfe190400 0x0 0x20>;
2283 reg = <0x0 0xfe198000 0x0 0x20>;
2288 reg = <0x0 0xfe1a8000 0x0 0x20>;
2293 reg = <0x0 0xfe1a8080 0x0 0x20>;
2298 reg = <0x0 0xfe1a8100 0x0 0x20>;
2304 reg = <0x0 0xfe000000 0x0 0x4000>;
2310 fifo-depth = <0x100>;
2317 reg = <0x00 0xfe230000 0x00 0x400>;
2333 0 286 324000
2338 0 620 324000
2343 0 350 324000
2370 debug_print_level = <0>;
2388 rockchip,low-temp = <0>;
2391 0 1560 75000
2394 1 80 0
2398 0 84000 0
2401 rockchip,pvtm-ch = <0 5>;
2415 bus-range = <0x0 0xf>;
2429 interrupt-map-mask = <0 0 0 7>;
2430 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
2431 <0 0 0 2 &pcie2x1_intc 1>,
2432 <0 0 0 3 &pcie2x1_intc 2>,
2433 <0 0 0 4 &pcie2x1_intc 3>;
2434 linux,pci-domain = <0>;
2439 msi-map = <0x0 &its 0x0 0x1000>;
2444 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
2445 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
2446 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000
2447 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
2448 reg = <0x3 0xc0000000 0x0 0x400000>,
2449 <0x0 0xfe260000 0x0 0x10000>;
2457 #address-cells = <0>;
2468 bus-range = <0x10 0x1f>;
2482 interrupt-map-mask = <0 0 0 7>;
2483 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
2484 <0 0 0 2 &pcie3x1_intc 1>,
2485 <0 0 0 3 &pcie3x1_intc 2>,
2486 <0 0 0 4 &pcie3x1_intc 3>;
2492 msi-map = <0x1000 &its 0x1000 0x1000>;
2497 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
2498 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
2499 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000
2500 0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
2501 reg = <0x3 0xc0400000 0x0 0x400000>,
2502 <0x0 0xfe270000 0x0 0x10000>;
2511 #address-cells = <0>;
2522 bus-range = <0x20 0x2f>;
2536 interrupt-map-mask = <0 0 0 7>;
2537 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
2538 <0 0 0 2 &pcie3x2_intc 1>,
2539 <0 0 0 3 &pcie3x2_intc 2>,
2540 <0 0 0 4 &pcie3x2_intc 3>;
2546 msi-map = <0x2000 &its 0x2000 0x1000>;
2551 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
2552 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
2553 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000
2554 0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
2555 reg = <0x3 0xc0800000 0x0 0x400000>,
2556 <0x0 0xfe280000 0x0 0x10000>;
2565 #address-cells = <0>;
2574 reg = <0x0 0xfe2a0000 0x0 0x10000>;
2582 reg = <0x0 0xfe2b0000 0x0 0x4000>;
2588 fifo-depth = <0x100>;
2597 reg = <0x0 0xfe2c0000 0x0 0x4000>;
2603 fifo-depth = <0x100>;
2611 reg = <0x0 0xfe300000 0x0 0x4000>;
2618 #size-cells = <0>;
2624 reg = <0x0 0xfe310000 0x0 0x10000>;
2642 reg = <0x0 0xfe330000 0x0 0x4000>;
2644 nandc_id = <0>;
2652 reg = <0x0 0xfe380000 0x0 0x4000>;
2666 reg = <0x0 0xfe388000 0x0 0x2000>;
2676 reg = <0x0 0xfe38c000 0x0 0x4000>;
2687 reg = <0x02 0x2>;
2690 reg = <0x08 0x1>;
2694 reg = <0x09 0x1>;
2695 bits = <0 4>;
2698 reg = <0x0a 0x10>;
2701 reg = <0x1a 0x1>;
2704 reg = <0x1b 0x1>;
2707 reg = <0x1c 0x1>;
2710 reg = <0x1d 0x1>;
2713 reg = <0x2a 0x2>;
2716 reg = <0x2e 0x1>;
2719 reg = <0x2f 0x1>;
2720 bits = <0 4>;
2723 reg = <0x30 0x1>;
2726 reg = <0x31 0x1>;
2727 bits = <0 4>;
2730 reg = <0x31 0x1>;
2734 reg = <0x32 0x1>;
2737 reg = <0x36 0x6>;
2740 reg = <0x3c 0x6>;
2743 reg = <0x42 0x6>;
2746 reg = <0x48 0x6>;
2752 reg = <0x0 0xfe400000 0x0 0x1000>;
2756 dmas = <&dmac1 0>;
2763 #sound-dai-cells = <0>;
2769 reg = <0x0 0xfe410000 0x0 0x1000>;
2779 #sound-dai-cells = <0>;
2781 pinctrl-0 = <&i2s1m0_sclktx
2798 reg = <0x0 0xfe420000 0x0 0x1000>;
2807 #sound-dai-cells = <0>;
2809 pinctrl-0 = <&i2s2m0_sclktx
2818 reg = <0x0 0xfe430000 0x0 0x1000>;
2829 #sound-dai-cells = <0>;
2831 pinctrl-0 = <&i2s3m0_sclk
2840 reg = <0x0 0xfe440000 0x0 0x1000>;
2846 pinctrl-0 = <&pdmm0_clk
2852 #sound-dai-cells = <0>;
2858 reg = <0x0 0xfe450000 0x0 0x10000>;
2863 rockchip,audio-src = <0>;
2864 rockchip,det-channel = <0>;
2865 rockchip,mode = <0>;
2866 #sound-dai-cells = <0>;
2872 reg = <0x0 0xfe460000 0x0 0x1000>;
2878 #sound-dai-cells = <0>;
2880 pinctrl-0 = <&spdifm0_tx>;
2886 reg = <0x0 0xfe470000 0x0 0x1000>;
2891 #sound-dai-cells = <0>;
2899 reg = <0x0 0xfe478000 0x0 0x1000>;
2904 pinctrl-0 = <&acodec_pins>;
2908 #sound-dai-cells = <0>;
2914 reg = <0x0 0xfe530000 0x0 0x4000>;
2925 reg = <0x0 0xfe550000 0x0 0x4000>;
2936 reg = <0x0 0xfe560000 0x0 0x10000>;
2939 pinctrl-0 = <&scr_pins>;
2947 …reg = <0x0 0xfe570000 0x0 0x1000>; // Default uses forlinx,rk3568-can-2.0 with forlinx_canfd.lo
2955 rockchip,tx-invalid-info = <0x40 0x0 0x0 0x0>;
2961 reg = <0x0 0xfe580000 0x0 0x1000>;
2969 rockchip,tx-invalid-info = <0x40 0x0 0x0 0x0>;
2975 reg = <0x0 0xfe590000 0x0 0x1000>;
2983 rockchip,tx-invalid-info = <0x40 0x0 0x0 0x0>;
2989 reg = <0x0 0xfe5a0000 0x0 0x1000>;
2994 pinctrl-0 = <&i2c1_xfer>;
2996 #size-cells = <0>;
3002 reg = <0x0 0xfe5b0000 0x0 0x1000>;
3007 pinctrl-0 = <&i2c2m0_xfer>;
3009 #size-cells = <0>;
3015 reg = <0x0 0xfe5c0000 0x0 0x1000>;
3020 pinctrl-0 = <&i2c3m0_xfer>;
3022 #size-cells = <0>;
3028 reg = <0x0 0xfe5d0000 0x0 0x1000>;
3033 pinctrl-0 = <&i2c4m0_xfer>;
3035 #size-cells = <0>;
3041 reg = <0x0 0xfe5e0000 0x0 0x1000>;
3046 pinctrl-0 = <&i2c5m0_xfer>;
3048 #size-cells = <0>;
3054 reg = <0x0 0xfe5f0000 0x0 0x1000>;
3062 reg = <0x0 0xfe600000 0x0 0x100>;
3071 reg = <0x0 0xfe610000 0x0 0x1000>;
3074 #size-cells = <0>;
3080 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
3088 reg = <0x0 0xfe620000 0x0 0x1000>;
3091 #size-cells = <0>;
3097 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
3105 reg = <0x0 0xfe630000 0x0 0x1000>;
3108 #size-cells = <0>;
3114 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
3122 reg = <0x0 0xfe640000 0x0 0x1000>;
3125 #size-cells = <0>;
3131 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
3139 reg = <0x0 0xfe650000 0x0 0x100>;
3147 pinctrl-0 = <&uart1m0_xfer>;
3153 reg = <0x0 0xfe660000 0x0 0x100>;
3161 pinctrl-0 = <&uart2m0_xfer>;
3167 reg = <0x0 0xfe670000 0x0 0x100>;
3175 pinctrl-0 = <&uart3m0_xfer>;
3181 reg = <0x0 0xfe680000 0x0 0x100>;
3189 pinctrl-0 = <&uart4m0_xfer>;
3195 reg = <0x0 0xfe690000 0x0 0x100>;
3203 pinctrl-0 = <&uart5m0_xfer>;
3209 reg = <0x0 0xfe6a0000 0x0 0x100>;
3217 pinctrl-0 = <&uart6m0_xfer>;
3223 reg = <0x0 0xfe6b0000 0x0 0x100>;
3231 pinctrl-0 = <&uart7m0_xfer>;
3237 reg = <0x0 0xfe6c0000 0x0 0x100>;
3245 pinctrl-0 = <&uart8m0_xfer>;
3251 reg = <0x0 0xfe6d0000 0x0 0x100>;
3259 pinctrl-0 = <&uart9m0_xfer>;
3265 reg = <0x0 0xfe6e0000 0x0 0x10>;
3268 pinctrl-0 = <&pwm4_pins>;
3276 reg = <0x0 0xfe6e0010 0x0 0x10>;
3279 pinctrl-0 = <&pwm5_pins>;
3287 reg = <0x0 0xfe6e0020 0x0 0x10>;
3290 pinctrl-0 = <&pwm6_pins>;
3298 reg = <0x0 0xfe6e0030 0x0 0x10>;
3303 pinctrl-0 = <&pwm7_pins>;
3311 reg = <0x0 0xfe6f0000 0x0 0x10>;
3314 pinctrl-0 = <&pwm8m0_pins>;
3322 reg = <0x0 0xfe6f0010 0x0 0x10>;
3325 pinctrl-0 = <&pwm9m0_pins>;
3333 reg = <0x0 0xfe6f0020 0x0 0x10>;
3336 pinctrl-0 = <&pwm10m0_pins>;
3344 reg = <0x0 0xfe6f0030 0x0 0x10>;
3349 pinctrl-0 = <&pwm11m0_pins>;
3357 reg = <0x0 0xfe700000 0x0 0x10>;
3360 pinctrl-0 = <&pwm12m0_pins>;
3368 reg = <0x0 0xfe700010 0x0 0x10>;
3371 pinctrl-0 = <&pwm13m0_pins>;
3379 reg = <0x0 0xfe700020 0x0 0x10>;
3382 pinctrl-0 = <&pwm14m0_pins>;
3390 reg = <0x0 0xfe700030 0x0 0x10>;
3395 pinctrl-0 = <&pwm15m0_pins>;
3403 reg = <0x0 0xfe710000 0x0 0x100>;
3417 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
3418 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
3420 pinctrl-0 = <&tsadc_gpio_func>;
3423 #size-cells = <0>;
3426 tsadc@0 {
3427 reg = <0>;
3440 reg = <0x0 0xfe720000 0x0 0x100>;
3453 reg = <0x0 0xfe780000 0x0 0x1000>;
3466 reg = <0x0 0xfe820000 0x0 0x100>;
3482 reg = <0x0 0xfe830000 0x0 0x100>;
3498 reg = <0x0 0xfe840000 0x0 0x100>;
3514 reg = <0x0 0xfe850000 0x0 0x10000>,
3515 <0x0 0xfe060000 0x0 0x10000>;
3520 #clock-cells = <0>;
3524 #phy-cells = <0>;
3530 reg = <0x0 0xfe860000 0x0 0x10000>,
3531 <0x0 0xfe070000 0x0 0x10000>;
3536 #clock-cells = <0>;
3540 #phy-cells = <0>;
3546 reg = <0x0 0xfe870000 0x0 0x1000>;
3584 reg = <0x0 0xfe8a0000 0x0 0x10000>;
3588 #clock-cells = <0>;
3596 #phy-cells = <0>;
3601 #phy-cells = <0>;
3608 reg = <0x0 0xfe8b0000 0x0 0x10000>;
3612 #clock-cells = <0>;
3617 #phy-cells = <0>;
3622 #phy-cells = <0>;
3629 reg = <0x0 0xfe8c0000 0x0 0x20000>;
3630 #phy-cells = <0>;
3650 reg = <0x0 0xfdd60000 0x0 0x100>;
3662 reg = <0x0 0xfe740000 0x0 0x100>;
3674 reg = <0x0 0xfe750000 0x0 0x100>;
3686 reg = <0x0 0xfe760000 0x0 0x100>;
3698 reg = <0x0 0xfe770000 0x0 0x100>;