Lines Matching +full:0 +full:xff3a0000
72 #clock-cells = <0>;
79 #clock-cells = <0>;
86 reg = <0 0xff100324 0 0x10>;
90 #clock-cells = <0>;
95 reg = <0 0xff100328 0 0x10>;
99 #clock-cells = <0>;
104 reg = <0 0xff10032c 0 0x10>;
108 #clock-cells = <0>;
113 reg = <0 0xff100334 0 0x10>;
117 #clock-cells = <0>;
122 reg = <0 0xff100324 0 0x10>;
126 #clock-cells = <0>;
131 reg = <0 0xff100338 0 0x10>;
135 #clock-cells = <0>;
140 #clock-cells = <0>;
141 clock-frequency = <0>;
147 #clock-cells = <0>;
148 clock-frequency = <0>;
154 #clock-cells = <0>;
155 clock-frequency = <0>;
161 reg = <0 0xff040070 0 0x4>;
163 #clock-cells = <0>;
170 reg = <0 0xff040070 0 0x4>;
172 #clock-cells = <0>;
179 reg = <0 0xff040070 0 0x4>;
181 #clock-cells = <0>;
189 #size-cells = <0>;
191 cpu0: cpu@0 {
194 reg = <0x0 0x0>;
205 reg = <0x0 0x1>;
216 reg = <0x0 0x2>;
227 reg = <0x0 0x3>;
241 arm,psci-suspend-param = <0x0010000>;
258 0 1280 0
265 rockchip,pvtm-offset = <0x634>;
270 rockchip,pvtm-temp-prop = <0 0>;
367 rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
368 <1 0x00a000a8 0x7c39>,
369 <2 0x00a000a8 0x7c39>,
370 <3 0x00a000a8 0x7c39>,
371 <4 0x00a000a5 0xb007>,
372 <5 0x00a000a8 0x7034>,
373 <6 0x00a000a8 0x7034>,
374 <7 0x00a000a8 0x7034>,
375 <8 0x00a000a8 0x7001>;
503 1 15 0
521 arm,smc-id = <0x82000010>;
523 #size-cells = <0>;
526 reg = <0x14>;
579 reg = <0x0 0x0 0x0 0x0>;
584 reg = <0x0 0x0 0x0 0x0>;
589 reg = <0x0 0x0 0x0 0x0>;
594 /* 0x110000 to 0x1f0000 is for ramoops */
595 reg = <0x0 0x110000 0x0 0xe0000>;
596 boot-log-size = <0x8000>; /* do not change */
597 boot-log-count = <0x1>; /* do not change */
598 console-size = <0x80000>;
599 pmsg-size = <0x30000>;
600 ftrace-size = <0x00000>;
601 record-size = <0x14000>;
764 thermal-sensors = <&tsadc 0>;
766 threshold: trip-point-0 {
815 reg = <0x0 0x0010f000 0x0 0x100>;
830 reg = <0x0 0xfe500000 0x0 0x400000>;
854 #address-cells = <0>;
856 reg = <0x0 0xfe901000 0 0x1000>,
857 <0x0 0xfe902000 0 0x2000>,
858 <0x0 0xfe904000 0 0x2000>,
859 <0x0 0xfe906000 0 0x2000>;
865 reg = <0x0 0xfed00000 0x0 0x40000>;
877 reg = <0x0 0xfed40000 0x0 0x40000>;
889 reg = <0x0 0xfed90000 0x0 0x2000>,
890 <0x0 0xfed92000 0x0 0x2000>,
891 <0x0 0xfed94000 0x0 0x2000>,
892 <0x0 0xfed96000 0x0 0x2000>;
897 reg = <0x0 0xfee03800 0x0 0x20>;
902 reg = <0x0 0xfee10000 0x0 0x20>;
907 reg = <0x0 0xfee10100 0x0 0x20>;
912 reg = <0x0 0xfee10200 0x0 0x20>;
917 reg = <0x0 0xfee10300 0x0 0x20>;
922 reg = <0x0 0xfee10400 0x0 0x20>;
927 reg = <0x0 0xfee20000 0x0 0x20>;
932 reg = <0x0 0xfee20100 0x0 0x20>;
937 reg = <0x0 0xfee30000 0x0 0x20>;
938 priority-init = <0x202>;
943 reg = <0x0 0xfee40000 0x0 0x20>;
948 reg = <0x0 0xfee50000 0x0 0x20>;
953 reg = <0x0 0xfee60000 0x0 0x20>;
958 reg = <0x0 0xfee70000 0x0 0x20>;
963 reg = <0x0 0xfee70100 0x0 0x20>;
968 reg = <0x0 0xfee80000 0x0 0x20>;
973 reg = <0x0 0xfee90000 0x0 0x20>;
978 reg = <0x0 0xfee90100 0x0 0x20>;
983 reg = <0x0 0xfee90200 0x0 0x20>;
988 reg = <0x0 0xfeea0000 0x0 0x20>;
993 reg = <0x0 0xfeea0100 0x0 0x20>;
998 reg = <0x0 0xfeeb0000 0x0 0x20>;
1003 reg = <0x0 0xfeeb0100 0x0 0x20>;
1008 reg = <0x0 0xfeeb0200 0x0 0x20>;
1013 reg = <0x0 0xfeeb0300 0x0 0x20>;
1018 reg = <0x0 0xfeeb0400 0x0 0x20>;
1023 reg = <0x0 0xfeeb0500 0x0 0x20>;
1028 reg = <0x0 0xfeeb0600 0x0 0x20>;
1033 reg = <0x0 0xfeeb0700 0x0 0x20>;
1038 reg = <0x0 0xfeeb0800 0x0 0x20>;
1043 reg = <0x0 0xff010000 0x0 0x10000>;
1047 offset = <0x220>;
1062 reg = <0x0 0xff030000 0x0 0x10000>;
1072 #size-cells = <0>;
1074 port@0 {
1075 reg = <0>;
1077 #size-cells = <0>;
1079 lvds_in_vp0: endpoint@0 {
1080 reg = <0>;
1091 reg = <0x0 0xff040000 0x0 0x10000>;
1096 reg = <0x0 0xff060000 0x0 0x30000>;
1101 pinctrl-0 = <&vo_pins>;
1106 #size-cells = <0>;
1108 port@0 {
1109 reg = <0>;
1111 #size-cells = <0>;
1113 rgb_in_vp0: endpoint@0 {
1114 reg = <0>;
1125 reg = <0x0 0xff090000 0x0 0x8000>;
1130 reg = <0x0 0xff098000 0x0 0x8000>;
1135 reg = <0x0 0xff100000 0x0 0x40000>;
1148 reg = <0x0 0xff200000 0x0 0x1000>;
1153 pinctrl-0 = <&i2c0_xfer>;
1155 #size-cells = <0>;
1161 reg = <0x0 0xff210000 0x0 0x100>;
1167 dmas = <&dmac 0>;
1173 reg = <0x0 0xff220000 0x0 0x1000>;
1176 #size-cells = <0>;
1182 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
1189 reg = <0x0 0xff230000 0x0 0x10>;
1193 pinctrl-0 = <&pwm0m0_pins>;
1201 reg = <0x0 0xff230010 0x0 0x10>;
1205 pinctrl-0 = <&pwm1m0_pins>;
1213 reg = <0x0 0xff230020 0x0 0x10>;
1217 pinctrl-0 = <&pwm2m0_pins>;
1225 reg = <0x0 0xff230030 0x0 0x10>;
1230 pinctrl-0 = <&pwm3m0_pins>;
1238 reg = <0x0 0xff258000 0x0 0x1000>;
1244 #size-cells = <0>;
1265 #size-cells = <0>;
1277 #size-cells = <0>;
1298 reg = <0x0 0xff290000 0x0 0x200>;
1308 reg = <0x0 0xff300000 0x0 0x10000>;
1330 0 760 0
1337 rockchip,pvtm-offset = <0x674>;
1342 rockchip,pvtm-temp-prop = <0 0>;
1410 reg = <0x0 0xff30a000 0x0 0x40>;
1416 #iommu-cells = <0>;
1422 reg = <0x0 0xff320000 0x0 0x4000>;
1451 0 780 0
1458 rockchip,pvtm-offset = <0x654>;
1463 rockchip,pvtm-temp-prop = <0 0>;
1517 reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>;
1523 rockchip,normal-rates = <198000000>, <0>, <396000000>;
1532 rockchip,taskqueue-node = <0>;
1533 rockchip,resetgroup-node = <0>;
1540 reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>;
1547 #iommu-cells = <0>;
1553 reg = <0x0 0xff360000 0x0 0x6000>;
1558 rockchip,normal-rates = <297000000>, <0>, <297000000>;
1574 reg = <0x0 0xff36f000 0x0 0x40>;
1581 #iommu-cells = <0>;
1587 reg = <0x0 0xff380000 0x0 0x10000>;
1601 reg = <0x0 0xff390000 0x0 0x10000>;
1615 reg = <0x0 0xff3a0000 0x0 0x10000>;
1629 reg = <0x0 0xff3b0000 0x0 0x10000>;
1643 reg = <0x0 0xff3c0000 0x0 0x10000>;
1654 reg = <0x0 0xff3d0000 0x0 0x10000>;
1665 reg = <0x0 0xff3e0000 0x0 0x800>;
1689 reg = <0x0 0xff3e0800 0x0 0x100>;
1696 #iommu-cells = <0>;
1702 reg = <0x0 0xff3f0000 0x0 0x7f00>;
1716 reg = <0x0 0xff3f7f00 0x0 0x100>;
1722 #iommu-cells = <0>;
1729 reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>;
1753 #size-cells = <0>;
1755 vp0: port@0 {
1757 #size-cells = <0>;
1758 reg = <0>;
1760 vp0_out_rgb: endpoint@0 {
1761 reg = <0>;
1780 reg = <0x0 0xff407e00 0x0 0x100>;
1785 #iommu-cells = <0>;
1793 reg = <0x0 0xff440000 0x0 0x1000>;
1805 reg = <0x0 0xff440f00 0x0 0x100>;
1810 #iommu-cells = <0>;
1817 reg = <0x0 0xff450000 0x0 0x400>;
1834 reg = <0x0 0xff450480 0x0 0x40>;
1841 #iommu-cells = <0>;
1846 reg = <0x00 0xff4c0000 0x00 0x400>;
1856 bus-range = <0x0 0xff>;
1871 interrupt-map-mask = <0 0 0 7>;
1872 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
1873 <0 0 0 2 &pcie2x1_intc 1>,
1874 <0 0 0 3 &pcie2x1_intc 2>,
1875 <0 0 0 4 &pcie2x1_intc 3>;
1876 linux,pci-domain = <0>;
1885 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
1886 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
1887 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
1888 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
1889 reg = <0x0 0xfe000000 0x0 0x400000>,
1890 <0x0 0xff500000 0x0 0x10000>;
1898 #address-cells = <0>;
1906 reg = <0x0 0xff640000 0x0 0x1000>;
1909 #size-cells = <0>;
1915 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1922 reg = <0x0 0xff650000 0x0 0x1000>;
1925 #size-cells = <0>;
1931 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1938 reg = <0x0 0xff670000 0x0 0x100>;
1950 reg = <0x0 0xff680000 0x0 0x100>;
1962 reg = <0x0 0xff690000 0x0 0x100>;
1974 reg = <0x0 0xff6a0000 0x0 0x100>;
1986 reg = <0x0 0xff6b0000 0x0 0x100>;
1998 reg = <0x0 0xff6c0000 0x0 0x100>;
2010 reg = <0x0 0xff6d0000 0x0 0x100>;
2022 reg = <0x0 0xff6e0000 0x0 0x100>;
2034 reg = <0x0 0xff6f0000 0x0 0x100>;
2046 reg = <0x0 0xff700000 0x0 0x10>;
2050 pinctrl-0 = <&pwm4m0_pins>;
2058 reg = <0x0 0xff700010 0x0 0x10>;
2062 pinctrl-0 = <&pwm5m0_pins>;
2070 reg = <0x0 0xff700020 0x0 0x10>;
2074 pinctrl-0 = <&pwm6m0_pins>;
2082 reg = <0x0 0xff700030 0x0 0x10>;
2087 pinctrl-0 = <&pwm7m0_pins>;
2095 reg = <0x0 0xff710000 0x0 0x10>;
2099 pinctrl-0 = <&pwm8m0_pins>;
2107 reg = <0x0 0xff710010 0x0 0x10>;
2111 pinctrl-0 = <&pwm9m0_pins>;
2119 reg = <0x0 0xff710020 0x0 0x10>;
2123 pinctrl-0 = <&pwm10m0_pins>;
2131 reg = <0x0 0xff710030 0x0 0x10>;
2136 pinctrl-0 = <&pwm11m0_pins>;
2144 reg = <0x0 0xff720000 0x0 0x10>;
2148 pinctrl-0 = <&pwm12m0_pins>;
2156 reg = <0x0 0xff720010 0x0 0x10>;
2160 pinctrl-0 = <&pwm13m0_pins>;
2168 reg = <0x0 0xff720020 0x0 0x10>;
2172 pinctrl-0 = <&pwm14m0_pins>;
2180 reg = <0x0 0xff720030 0x0 0x10>;
2185 pinctrl-0 = <&pwm15m0_pins>;
2193 reg = <0x0 0xff730000 0x0 0x100>;
2205 reg = <0x0 0xff740000 0x0 0x10000>;
2208 #clock-cells = <0>;
2214 #phy-cells = <0>;
2223 #phy-cells = <0>;
2232 reg = <0x0 0xff750000 0x0 0x100>;
2248 reg = <0x0 0xff800000 0x0 0x1000>;
2259 pinctrl-0 = <&i2s0m0_lrck
2266 #sound-dai-cells = <0>;
2272 reg = <0x0 0xff810000 0x0 0x1000>;
2283 pinctrl-0 = <&i2s1m0_lrck
2293 #sound-dai-cells = <0>;
2299 reg = <0x0 0xff820000 0x0 0x1000>;
2310 pinctrl-0 = <&i2s2m0_lrck
2314 #sound-dai-cells = <0>;
2320 reg = <0x0 0xff830000 0x0 0x1000>;
2328 pinctrl-0 = <&pdmm0_clk0
2334 #sound-dai-cells = <0>;
2340 reg = <0x0 0xff840000 0x0 0x1000>;
2348 #sound-dai-cells = <0>;
2350 pinctrl-0 = <&spdifm0_pins>;
2356 reg = <0x0 0xff850000 0x0 0x1000>;
2363 pinctrl-0 = <&dsm_pins>;
2364 #sound-dai-cells = <0>;
2370 reg = <0x0 0xff860000 0x0 0x10000>;
2377 #size-cells = <0>;
2383 reg = <0x0 0xff870000 0x0 0x10000>;
2402 reg = <0x0 0xff880000 0x0 0x10000>;
2410 fifo-depth = <0x100>;
2417 reg = <0x0 0xff890000 0x0 0x10000>;
2425 fifo-depth = <0x100>;
2431 reg = <0x0 0xff8a0000 0x0 0x2000>;
2446 reg = <0x0 0xff8e0000 0x0 0x200>;
2457 reg = <0x0 0xff930000 0x0 0x4000>;
2471 reg = <0x02 0x2>;
2474 reg = <0x08 0x1>;
2478 reg = <0x09 0x1>;
2479 bits = <0 2>;
2482 reg = <0x09 0x1>;
2486 reg = <0x0a 0x10>;
2489 reg = <0x1a 0x1>;
2492 reg = <0x1b 0x1>;
2495 reg = <0x1c 0x1>;
2498 reg = <0x1d 0x1>;
2501 reg = <0x2a 0x1>;
2504 reg = <0x2b 0x1>;
2507 reg = <0x2c 0x1>;
2511 reg = <0x2d 0x1>;
2514 reg = <0x2e 0x6>;
2517 reg = <0x34 0x6>;
2520 reg = <0x3a 0x6>;
2523 reg = <0x40 0x6>;
2526 reg = <0x46 0x2>;
2529 reg = <0x48 0x2>;
2532 reg = <0x4a 0x2>;
2538 reg = <0x0 0xff990000 0x0 0x4000>;
2549 reg = <0x0 0xff9a0000 0x0 0x4000>;
2561 reg = <0x0 0xff9e0000 0x0 0x100>;
2568 reg = <0x0 0xffa00000 0x0 0x1000>;
2573 pinctrl-0 = <&i2c1m0_xfer>;
2575 #size-cells = <0>;
2581 reg = <0x0 0xffa10000 0x0 0x1000>;
2586 pinctrl-0 = <&i2c2m0_xfer>;
2588 #size-cells = <0>;
2594 reg = <0x0 0xffa20000 0x0 0x1000>;
2599 pinctrl-0 = <&i2c3m0_xfer>;
2601 #size-cells = <0>;
2607 reg = <0x0 0xffa30000 0x0 0x1000>;
2612 pinctrl-0 = <&i2c4m0_xfer>;
2614 #size-cells = <0>;
2620 reg = <0x0 0xffa40000 0x0 0x1000>;
2625 pinctrl-0 = <&i2c5m0_xfer>;
2627 #size-cells = <0>;
2633 reg = <0x0 0xffa50000 0x0 0x20>;
2641 reg = <0x0 0xffa60000 0x0 0x100>;
2650 reg = <0x0 0xffa70000 0x0 0x400>;
2661 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2662 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2670 reg = <0x0 0xffa80000 0x0 0x10000>;
2693 #address-cells = <0x1>;
2694 #size-cells = <0x0>;
2700 snps,blen = <0 0 0 0 16 8 4>;
2716 reg = <0x0 0xffaa0000 0x0 0x100>;
2729 reg = <0x0 0xffae0000 0x0 0x200>;
2739 reg = <0x0 0xffb10000 0x0 0x10000>;
2749 #size-cells = <0>;
2754 #size-cells = <0>;
2756 dsi_in: port@0 {
2757 reg = <0>;
2759 #size-cells = <0>;
2761 dsi_in_vp0: endpoint@0 {
2762 reg = <0>;
2773 reg = <0x0 0xffb20000 0x0 0x10000>,
2774 <0x0 0xffb10000 0x0 0x10000>;
2779 #clock-cells = <0>;
2782 #phy-cells = <0>;
2788 reg = <0x0 0xffb30000 0x0 0x10000>;
2804 #address-cells = <0x1>;
2805 #size-cells = <0x0>;
2818 reg = <0x0 0xff260000 0x0 0x100>;
2819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2824 gpio-ranges = <&pinctrl 0 0 32>;
2831 reg = <0x0 0xff620000 0x0 0x100>;
2837 gpio-ranges = <&pinctrl 0 32 32>;
2844 reg = <0x0 0xff630000 0x0 0x100>;
2850 gpio-ranges = <&pinctrl 0 64 32>;
2857 reg = <0x0 0xffac0000 0x0 0x100>;
2863 gpio-ranges = <&pinctrl 0 96 32>;
2870 reg = <0x0 0xffad0000 0x0 0x100>;
2876 gpio-ranges = <&pinctrl 0 128 32>;
2887 (0
2897 (0