Lines Matching +full:0 +full:xff410000
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
58 reg = <0x0 0x1>;
71 reg = <0x0 0x2>;
84 reg = <0x0 0x3>;
100 arm,psci-suspend-param = <0x0010000>;
157 reg = <0x0 0xff1f0000 0x0 0x4000>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
228 #clock-cells = <0>;
235 reg = <0x0 0xff000000 0x0 0x1000>;
241 #sound-dai-cells = <0>;
247 reg = <0x0 0xff010000 0x0 0x1000>;
253 #sound-dai-cells = <0>;
259 reg = <0x0 0xff020000 0x0 0x1000>;
263 dmas = <&dmac 0>, <&dmac 1>;
265 #sound-dai-cells = <0>;
271 reg = <0x0 0xff030000 0x0 0x1000>;
278 pinctrl-0 = <&spdifm2_tx>;
279 #sound-dai-cells = <0>;
285 reg = <0x0 0xff040000 0x0 0x1000>;
291 pinctrl-0 = <&pdmm0_clk
306 reg = <0x0 0xff100000 0x0 0x1000>;
323 #size-cells = <0>;
339 offset = <0x5c8>;
349 reg = <0x0 0xff110000 0x0 0x100>;
356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
364 reg = <0x0 0xff120000 0x0 0x100>;
371 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
379 reg = <0x0 0xff130000 0x0 0x100>;
386 pinctrl-0 = <&uart2m1_xfer>;
394 reg = <0x0 0xff150000 0x0 0x1000>;
397 #size-cells = <0>;
401 pinctrl-0 = <&i2c0_xfer>;
407 reg = <0x0 0xff160000 0x0 0x1000>;
410 #size-cells = <0>;
414 pinctrl-0 = <&i2c1_xfer>;
420 reg = <0x0 0xff170000 0x0 0x1000>;
423 #size-cells = <0>;
427 pinctrl-0 = <&i2c2_xfer>;
433 reg = <0x0 0xff180000 0x0 0x1000>;
436 #size-cells = <0>;
440 pinctrl-0 = <&i2c3_xfer>;
446 reg = <0x0 0xff190000 0x0 0x1000>;
449 #size-cells = <0>;
455 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
461 reg = <0x0 0xff1a0000 0x0 0x100>;
468 reg = <0x0 0xff1b0000 0x0 0x10>;
472 pinctrl-0 = <&pwm0_pin>;
479 reg = <0x0 0xff1b0010 0x0 0x10>;
483 pinctrl-0 = <&pwm1_pin>;
490 reg = <0x0 0xff1b0020 0x0 0x10>;
494 pinctrl-0 = <&pwm2_pin>;
501 reg = <0x0 0xff1b0030 0x0 0x10>;
506 pinctrl-0 = <&pwmir_pin>;
517 thermal-sensors = <&tsadc 0>;
553 reg = <0x0 0xff250000 0x0 0x100>;
560 pinctrl-0 = <&otp_pin>;
572 reg = <0x0 0xff260000 0x0 0x50>;
577 rockchip,efuse-size = <0x20>;
581 reg = <0x07 0x10>;
584 reg = <0x17 0x1>;
587 reg = <0x19 0x1>;
590 reg = <0x1a 0x1>;
597 reg = <0x0 0xff280000 0x0 0x100>;
609 reg = <0x0 0xff300000 0x0 0x30000>;
631 reg = <0x0 0xff330200 0 0x100>;
636 #iommu-cells = <0>;
642 reg = <0x0 0xff340800 0x0 0x40>;
647 #iommu-cells = <0>;
653 reg = <0x0 0xff350000 0x0 0x800>;
664 reg = <0x0 0xff350800 0x0 0x40>;
669 #iommu-cells = <0>;
675 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
680 #iommu-cells = <0>;
686 reg = <0x0 0xff370000 0x0 0x3efc>;
697 #size-cells = <0>;
699 vop_out_hdmi: endpoint@0 {
700 reg = <0>;
708 reg = <0x0 0xff373f00 0x0 0x100>;
713 #iommu-cells = <0>;
719 reg = <0x0 0xff3c0000 0x0 0x20000>;
732 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
734 #sound-dai-cells = <0>;
748 reg = <0x0 0xff410000 0x0 0x1000>;
752 #sound-dai-cells = <0>;
758 reg = <0x0 0xff430000 0x0 0x10000>;
763 #clock-cells = <0>;
766 #phy-cells = <0>;
772 reg = <0x0 0xff440000 0x0 0x1000>;
804 <0>, <61440000>,
805 <0>, <24000000>,
825 reg = <0x0 0xff450000 0x0 0x10000>;
831 reg = <0x100 0x10>;
835 #clock-cells = <0>;
841 #phy-cells = <0>;
851 #phy-cells = <0>;
861 reg = <0x0 0xff500000 0x0 0x4000>;
866 fifo-depth = <0x100>;
873 reg = <0x0 0xff510000 0x0 0x4000>;
878 fifo-depth = <0x100>;
885 reg = <0x0 0xff520000 0x0 0x4000>;
890 fifo-depth = <0x100>;
897 reg = <0x0 0xff540000 0x0 0x10000>;
911 snps,txpbl = <0x4>;
917 reg = <0x0 0xff550000 0x0 0x10000>;
933 snps,txpbl = <0x4>;
940 #size-cells = <0>;
942 phy: ethernet-phy@0 {
944 reg = <0>;
948 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
957 reg = <0x0 0xff580000 0x0 0x40000>;
972 reg = <0x0 0xff5c0000 0x0 0x10000>;
982 reg = <0x0 0xff5d0000 0x0 0x10000>;
992 reg = <0x0 0xff600000 0x0 0x100000>;
1013 #address-cells = <0>;
1015 reg = <0x0 0xff811000 0 0x1000>,
1016 <0x0 0xff812000 0 0x2000>,
1017 <0x0 0xff814000 0 0x2000>,
1018 <0x0 0xff816000 0 0x2000>;
1032 reg = <0x0 0xff210000 0x0 0x100>;
1045 reg = <0x0 0xff220000 0x0 0x100>;
1058 reg = <0x0 0xff230000 0x0 0x100>;
1071 reg = <0x0 0xff240000 0x0 0x100>;
1179 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1180 <0 RK_PA6 2 &pcfg_pull_none>;
1184 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1185 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1191 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1192 <0 RK_PA6 1 &pcfg_pull_none>;
1196 pdm-0 {
1300 uart2-0 {
1314 spi0-0 {
1427 i2s2-0 {
1498 spdif-0 {
1500 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1512 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1516 sdmmc0-0 {
1528 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1532 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1683 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1688 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1696 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1766 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1768 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1770 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1772 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1774 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1776 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1778 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1805 <0 RK_PB3 1 &pcfg_pull_none>,
1807 <0 RK_PB4 1 &pcfg_pull_none>,
1809 <0 RK_PD0 1 &pcfg_pull_none>,
1811 <0 RK_PC3 1 &pcfg_pull_none>,
1813 <0 RK_PC0 1 &pcfg_pull_none>,
1815 <0 RK_PC1 1 &pcfg_pull_none>;
1821 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1825 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1852 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1856 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1860 cif-0 {