Lines Matching +full:0 +full:xff3a0000
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
69 reg = <0x0 0x1>;
83 arm,psci-suspend-param = <0x0010000>;
92 arm,psci-suspend-param = <0x1010000>;
105 rockchip,low-temp = <0>;
109 0 1608 50000
118 0 69000 0
124 rockchip,pvtm-ch = <0 0>;
212 bus-id = <0>;
213 cfg-val = <0x1e0>;
214 enable-msk = <0x407f>;
219 cfg-val = <0x12c0>;
220 enable-msk = <0x41ff>;
225 cfg-val = <0x12c0>;
226 enable-msk = <0x4005>;
231 cfg-val = <0x12c0>;
232 enable-msk = <0x4001>;
237 cfg-val = <0x12c0>;
238 enable-msk = <0x4001>;
247 #clock-cells = <0>;
264 rockchip,sleep-debug-en = <0>;
266 (0
275 (0
294 #clock-cells = <0>;
301 #clock-cells = <0>;
303 pinctrl-0 = <&clkin_32k>;
310 bus-range = <0x0 0x1f>;
322 linux,pci-domain = <0>;
325 msi-map = <0x0 &its 0x0 0x1000>;
330 pinctrl-0 = <&pcie_clkreq>;
332 ranges = <0x00000800 0x0 0xf8000000 0x0 0xf8000000 0x0 0x800000
333 0x83000000 0x0 0xf8800000 0x0 0xf8800000 0x0 0x3700000
334 0x81000000 0x0 0xfbf00000 0x0 0xfbf00000 0x0 0x100000>;
335 reg = <0x0 0xfc000000 0x0 0x400000>,
336 <0x0 0xfc400000 0x0 0x10000>;
374 reg = <0x0 0xfd000000 0x0 0x200000>;
395 reg = <0x0 0xfe000000 0x0 0x1000>;
402 #size-cells = <0>;
418 #size-cells = <0>;
420 port@0 {
421 reg = <0>;
434 reg = <0x0 0xfe010000 0x0 0x8000>;
440 reg = <0x100 0x10>;
443 #clock-cells = <0>;
450 #phy-cells = <0>;
457 #phy-cells = <0>;
470 reg = <0x0 0xfe018000 0x0 0x8000>;
475 reg = <0x0 0xfe020000 0x0 0x1000>;
482 #size-cells = <0>;
494 offset = <0x200>;
507 reg = <0x0 0xfe040000 0x0 0x1000>;
512 reg = <0x0 0xfe050000 0x0 0x1000>;
519 #size-cells = <0>;
522 pvtm@0 {
523 reg = <0>;
532 reg = <0x0 0xfe850000 0x0 0x20>;
537 reg = <0x0 0xfe880000 0x0 0x20>;
543 reg = <0x0 0xfe890000 0x0 0x20>;
549 reg = <0x0 0xfe890080 0x0 0x20>;
555 reg = <0x0 0xfe8a0000 0x0 0x20>;
560 reg = <0x0 0xfe8a0080 0x0 0x20>;
565 reg = <0x0 0xfe8a0100 0x0 0x20>;
570 reg = <0x0 0xfe8a0180 0x0 0x20>;
575 reg = <0x0 0xfe8b0000 0x0 0x20>;
580 reg = <0x0 0xfe8b0080 0x0 0x20>;
585 reg = <0x0 0xfe8c0000 0x0 0x20>;
590 reg = <0x0 0xfec00000 0x0 0x200000>;
593 ranges = <0 0x0 0xfec00000 0x200000>;
595 ddr-sram@0 {
596 reg = <0x0 0x8000>;
600 reg = <0x1c0000 0x40000>;
606 reg = <0 0xff040000 0 0x10000>;
618 reg = <0x0 0xff100000 0 0x10000>, /* GICD */
619 <0x0 0xff140000 0 0xc0000>, /* GICR */
620 <0x0 0xff300000 0 0x10000>, /* GICC */
621 <0x0 0xff310000 0 0x10000>, /* GICH */
622 <0x0 0xff320000 0 0x10000>; /* GICV */
627 reg = <0x0 0xff120000 0x0 0x20000>;
633 reg = <0x0 0xff3b0000 0x0 0x50>;
640 rockchip,efuse-size = <0x20>;
644 reg = <0x07 0x10>;
647 reg = <0x17 0x1>;
650 reg = <0x18 0x1>;
653 reg = <0x19 0x1>;
656 reg = <0x1c 0x1>;
663 reg = <0x0 0xff350000 0x0 0x5000>;
688 reg = <0x0 0xff360000 0x0 0x4000>;
698 reg = <0x0 0xff370000 0x0 0x500>;
702 #clock-cells = <0>;
705 #phy-cells = <0>;
712 reg = <0x0 0xff380000 0x0 0x10000>;
735 thermal-sensors = <&tsadc 0>;
738 threshold: trip-point-0 {
780 reg = <0x0 0xff3a0000 0x0 0x100>;
796 reg = <0x0 0xff3c0000 0x0 0x100>;
808 reg = <0x0 0xff3d0000 0x0 0x10>;
811 pinctrl-0 = <&pwm0_pin>;
819 reg = <0x0 0xff3d0010 0x0 0x10>;
822 pinctrl-0 = <&pwm1_pin>;
830 reg = <0x0 0xff3d0020 0x0 0x10>;
833 pinctrl-0 = <&pwm2_pin>;
841 reg = <0x0 0xff3d0030 0x0 0x10>;
844 pinctrl-0 = <&pwm3_pin>;
852 reg = <0x0 0xff3d8000 0x0 0x10>;
855 pinctrl-0 = <&pwm4_pin>;
863 reg = <0x0 0xff3d8010 0x0 0x10>;
866 pinctrl-0 = <&pwm5_pin>;
874 reg = <0x0 0xff3d8020 0x0 0x10>;
877 pinctrl-0 = <&pwm6_pin>;
885 reg = <0x0 0xff3d8030 0x0 0x10>;
888 pinctrl-0 = <&pwm7_pin>;
896 reg = <0x0 0xff3e0000 0x0 0x1000>;
902 #size-cells = <0>;
968 reg = <0x0 0xff410000 0x0 0x1000>;
973 pinctrl-0 = <&i2c0_xfer>;
975 #size-cells = <0>;
981 reg = <0x0 0xff4e0000 0x0 0x4000>;
991 reg = <0x0 0xff430000 0x0 0x100>;
997 dmas = <&dmac 0>, <&dmac 1>;
999 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
1005 reg = <0x0 0xff500000 0x0 0x1000>;
1010 pinctrl-0 = <&i2c1_xfer>;
1012 #size-cells = <0>;
1018 reg = <0x0 0xff504000 0x0 0x1000>;
1023 pinctrl-0 = <&i2c2m0_xfer>;
1025 #size-cells = <0>;
1031 reg = <0x0 0xff508000 0x0 0x1000>;
1036 pinctrl-0 = <&i2c3_xfer>;
1038 #size-cells = <0>;
1044 reg = <0x0 0xff50c000 0x0 0x1000>;
1049 pinctrl-0 = <&i2c4_xfer>;
1051 #size-cells = <0>;
1057 reg = <0x0 0xff510000 0x0 0x1000>;
1062 pinctrl-0 = <&i2c5_xfer>;
1064 #size-cells = <0>;
1070 reg = <0x0 0xff520000 0x0 0x1000>;
1073 #size-cells = <0>;
1078 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
1085 reg = <0x0 0xff530000 0x0 0x1000>;
1088 #size-cells = <0>;
1093 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
1100 reg = <0x0 0xff540000 0x0 0x100>;
1108 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>;
1114 reg = <0x0 0xff550000 0x0 0x100>;
1122 pinctrl-0 = <&uart2m0_xfer>;
1128 reg = <0x0 0xff560000 0x0 0x100>;
1136 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>;
1142 reg = <0x0 0xff570000 0x0 0x100>;
1150 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
1156 reg = <0x0 0xff580000 0x0 0x1000>;
1159 #size-cells = <0>;
1164 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>;
1171 reg = <0x0 0xff5a0000 0x0 0x100>;
1179 pinctrl-0 = <&uart5_xfer>;
1185 reg = <0x0 0xff5b0000 0x0 0x100>;
1193 pinctrl-0 = <&uart6_xfer>;
1199 reg = <0x0 0xff5c0000 0x0 0x100>;
1207 pinctrl-0 = <&uart7_xfer>;
1213 reg = <0x0 0xff5d0000 0x0 0x10>;
1216 pinctrl-0 = <&pwm8_pin>;
1224 reg = <0x0 0xff5d0010 0x0 0x10>;
1227 pinctrl-0 = <&pwm9_pin>;
1235 reg = <0x0 0xff5d0020 0x0 0x10>;
1238 pinctrl-0 = <&pwm10_pin>;
1246 reg = <0x0 0xff5d0030 0x0 0x10>;
1249 pinctrl-0 = <&pwm11_pin>;
1257 reg = <0x0 0xff630000 0x0 0x4000>;
1269 reg = <0x0 0xff640000 0x0 0x1000>;
1274 reg = <0x0 0xff700000 0x0 0x1000>;
1282 reg = <0x0 0xff720000 0x0 0x100>;
1290 reg = <0x0 0xff7e0000 0x0 0x1000>;
1301 pinctrl-0 = <&i2s0_8ch_sclktx
1319 reg = <0x0 0xff7f0000 0x0 0x1000>;
1328 pinctrl-0 = <&i2s1_2ch_sclk
1337 reg = <0x0 0xff800000 0x0 0x1000>;
1345 pinctrl-0 = <&pdm_clk
1356 reg = <0x0 0xff810000 0x0 0x10000>;
1362 rockchip,audio-src = <0>;
1363 rockchip,det-channel = <0>;
1369 reg = <0x00 0xff9c0000 0x00 0x400>;
1378 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1398 auto-freq-en = <0>;
1411 rockchip,low-temp = <0>;
1452 dev_mode = <0>;
1453 reg = <0x0 0xffaf0000 0x0 0x1000>;
1463 reg = <0x0 0xffae0000 0x0 0x200>;
1484 reg = <0x0 0xffae0800 0x0 0x100>;
1490 #iommu-cells = <0>;
1496 reg = <0x0 0xffb00000 0x0 0x200>;
1508 #size-cells = <0>;
1510 vop_lite_out_dsi: endpoint@0 {
1511 reg = <0>;
1524 reg = <0x0 0xffb00f00 0x0 0x100>;
1530 #iommu-cells = <0>;
1536 reg = <0x0 0xffb10000 0x0 0x100>;
1548 reg = <0x0 0xffb20000 0x0 0x500>;
1564 #size-cells = <0>;
1579 reg = <0x0 0xffb30000 0x0 0x500>;
1590 #size-cells = <0>;
1604 reg = <0x0 0xffb40000 0x0 0x500>;
1616 #size-cells = <0>;
1618 vop_raw_out_csi: endpoint@0 {
1619 reg = <0>;
1627 reg = <0x0 0xffb40f00 0x0 0x100>;
1633 #iommu-cells = <0>;
1639 reg = <0x0 0xffb50000 0x0 0x8000>;
1656 reg = <0x0 0xffb58000 0x0 0x100>;
1664 #iommu-cells = <0>;
1670 reg = <0x0 0xffb80000 0x0 0x800>;
1681 allocator = <1>; /* 0 means ion, 1 means drm */
1687 reg = <0x0 0xffb80800 0x0 0x100>;
1693 #iommu-cells = <0>;
1699 reg = <0x0 0xffc60000 0x0 0x4000>;
1704 fifo-depth = <0x100>;
1707 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
1713 reg = <0x0 0xffbc0000 0x0 0x1000>;
1739 rockchip,low-temp = <0>;
1743 0 792 50000
1752 0 69000 0
1756 rockchip,pvtm-ch = <0 0>;
1785 reg = <0x0 0xffc50000 0x0 0x4000>;
1796 reg = <0x0 0xffcf0000 0x0 0x4000>;
1801 fifo-depth = <0x100>;
1804 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_detn>;
1810 reg = <0x0 0xffd00000 0x0 0x4000>;
1815 fifo-depth = <0x100>;
1818 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1824 reg = <0x0 0xffd80000 0x0 0x10000>;
1837 reg = <0x0 0xffd90000 0x0 0x10000>;
1850 reg = <0x0 0xffdd0000 0x0 0x10000>;
1864 pinctrl-0 = <&rgmii_pins>;
1888 reg = <0x0 0xff4c0000 0x0 0x100>;
1900 reg = <0x0 0xff690000 0x0 0x100>;
1912 reg = <0x0 0xff6a0000 0x0 0x100>;
1924 reg = <0x0 0xff6b0000 0x0 0x100>;
1936 reg = <0x0 0xff6c0000 0x0 0x100>;
2186 <0 RK_PB1 1 &pcfg_pull_none_2ma_smt>,
2188 <0 RK_PB0 1 &pcfg_pull_none_2ma_smt>;
2196 <0 RK_PC1 1 &pcfg_pull_none_2ma_smt>,
2198 <0 RK_PC0 1 &pcfg_pull_none_2ma_smt>;
2468 <0 RK_PC6 1 &pcfg_pull_none >;
2508 <0 RK_PB7 1 &pcfg_pull_none_2ma>;
2515 <0 RK_PC3 1 &pcfg_pull_none_2ma>;
2522 <0 RK_PC5 1 &pcfg_pull_none_2ma>;
2529 <0 RK_PC4 1 &pcfg_pull_none_2ma>;
2613 <0 RK_PA3 1 &pcfg_pull_none>;
2875 <0 RK_PB3 1 &pcfg_pull_up_2ma>,
2877 <0 RK_PB2 1 &pcfg_pull_up_2ma>;
2882 <0 RK_PB4 1 &pcfg_pull_none>;
2887 <0 RK_PB5 1 &pcfg_pull_none>;
2949 <0 RK_PC4 2 &pcfg_pull_up_2ma>,
2951 <0 RK_PC3 2 &pcfg_pull_up_2ma>;
2956 <0 RK_PC6 2 &pcfg_pull_none>;
2961 <0 RK_PC7 2 &pcfg_pull_none>;
3018 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
3023 <0 RK_PA6 2 &pcfg_pull_none>;
3030 <0 RK_PC2 1 &pcfg_pull_none>;
3035 <0 RK_PC2 1 &pcfg_pull_none>;