Lines Matching +full:rk3328 +full:- +full:codec
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rv1126-cru.h>
7 #include <dt-bindings/power/rv1126-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rv1126.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include "rv1126-dram-default-timing.dtsi"
19 #address-cells = <1>;
20 #size-cells = <1>;
24 interrupt-parent = <&gic>;
49 #address-cells = <1>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a7";
56 enable-method = "psci";
58 operating-points-v2 = <&cpu0_opp_table>;
59 dynamic-power-coefficient = <60>;
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP>;
66 compatible = "arm,cortex-a7";
68 enable-method = "psci";
70 operating-points-v2 = <&cpu0_opp_table>;
71 dynamic-power-coefficient = <60>;
72 cpu-idle-states = <&CPU_SLEEP>;
77 compatible = "arm,cortex-a7";
79 enable-method = "psci";
81 operating-points-v2 = <&cpu0_opp_table>;
82 dynamic-power-coefficient = <60>;
83 cpu-idle-states = <&CPU_SLEEP>;
88 compatible = "arm,cortex-a7";
90 enable-method = "psci";
92 operating-points-v2 = <&cpu0_opp_table>;
93 dynamic-power-coefficient = <60>;
94 cpu-idle-states = <&CPU_SLEEP>;
97 idle-states {
98 entry-method = "psci";
100 CPU_SLEEP: cpu-sleep {
101 compatible = "arm,idle-state";
102 local-timer-stop;
103 arm,psci-suspend-param = <0x0010000>;
104 entry-latency-us = <120>;
105 exit-latency-us = <250>;
106 min-residency-us = <900>;
112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points-v2";
114 opp-shared;
116 nvmem-cells = <&cpu_leakage>, <&cpu_performance>;
117 nvmem-cell-names = "leakage", "performance";
119 rockchip,reboot-freq = <816000>;
121 rockchip,temp-freq-table = <
126 rockchip,bin-scaling-sel = <
130 rockchip,bin-voltage-sel = <
133 rockchip,pvtm-voltage-sel = <
139 rockchip,pvtm-freq = <408000>;
140 rockchip,pvtm-volt = <800000>;
141 rockchip,pvtm-ch = <0 0>;
142 rockchip,pvtm-sample-time = <1000>;
143 rockchip,pvtm-number = <10>;
144 rockchip,pvtm-error = <1000>;
145 rockchip,pvtm-ref-temp = <37>;
146 rockchip,pvtm-temp-prop = <(-40) 13>;
147 rockchip,pvtm-thermal-zone = "cpu-thermal";
149 opp-408000000 {
150 opp-hz = /bits/ 64 <408000000>;
151 opp-microvolt = <725000 725000 1000000>;
152 opp-microvolt-L0 = <725000 725000 1000000>;
153 clock-latency-ns = <40000>;
155 opp-600000000 {
156 opp-hz = /bits/ 64 <600000000>;
157 opp-microvolt = <725000 725000 1000000>;
158 opp-microvolt-L0 = <725000 725000 1000000>;
159 clock-latency-ns = <40000>;
161 opp-816000000 {
162 opp-hz = /bits/ 64 <816000000>;
163 opp-microvolt = <725000 725000 1000000>;
164 opp-microvolt-L0 = <750000 750000 1000000>;
165 clock-latency-ns = <40000>;
166 opp-suspend;
168 opp-1008000000 {
169 opp-hz = /bits/ 64 <1008000000>;
170 opp-microvolt = <775000 775000 1000000>;
171 opp-microvolt-L0 = <800000 800000 1000000>;
172 opp-microvolt-L1 = <775000 775000 1000000>;
173 opp-microvolt-L2 = <775000 775000 1000000>;
174 opp-microvolt-L3 = <750000 750000 1000000>;
175 opp-microvolt-L4 = <725000 725000 1000000>;
176 clock-latency-ns = <40000>;
178 opp-1200000000 {
179 opp-hz = /bits/ 64 <1200000000>;
180 opp-microvolt = <850000 850000 1000000>;
181 opp-microvolt-L0 = <875000 875000 1000000>;
182 opp-microvolt-L1 = <850000 850000 1000000>;
183 opp-microvolt-L2 = <850000 850000 1000000>;
184 opp-microvolt-L3 = <825000 825000 1000000>;
185 opp-microvolt-L4 = <800000 800000 1000000>;
186 clock-latency-ns = <40000>;
188 opp-1296000000 {
189 opp-hz = /bits/ 64 <1296000000>;
190 opp-microvolt = <875000 875000 1000000>;
191 opp-microvolt-L0 = <925000 925000 1000000>;
192 opp-microvolt-L1 = <875000 875000 1000000>;
193 opp-microvolt-L2 = <875000 875000 1000000>;
194 opp-microvolt-L3 = <850000 850000 1000000>;
195 opp-microvolt-L4 = <825000 825000 1000000>;
196 clock-latency-ns = <40000>;
198 opp-1416000000 {
199 opp-hz = /bits/ 64 <1416000000>;
200 opp-microvolt = <925000 925000 1000000>;
201 opp-microvolt-L0 = <975000 975000 1000000>;
202 opp-microvolt-L1 = <925000 925000 1000000>;
203 opp-microvolt-L2 = <925000 925000 1000000>;
204 opp-microvolt-L3 = <900000 900000 1000000>;
205 opp-microvolt-L4 = <875000 875000 1000000>;
206 clock-latency-ns = <40000>;
208 opp-1512000000 {
209 opp-hz = /bits/ 64 <1512000000>;
210 opp-microvolt = <975000 975000 1000000>;
211 opp-microvolt-L1 = <975000 975000 1000000>;
212 opp-microvolt-L2 = <950000 950000 1000000>;
213 opp-microvolt-L3 = <925000 925000 1000000>;
214 opp-microvolt-L4 = <900000 900000 1000000>;
215 clock-latency-ns = <40000>;
221 nvmem-cells = <&otp_id>, <&otp_cpu_code>;
222 nvmem-cell-names = "id", "cpu-code";
225 arm-pmu {
226 compatible = "arm,cortex-a7-pmu";
231 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
234 bus_soc: bus-soc {
235 compatible = "rockchip,rv1126-bus";
236 rockchip,busfreq-policy = "smc";
237 soc-bus0 {
238 bus-id = <0>;
239 cfg-val = <0x00300020>;
240 enable-msk = <0x7144>;
243 soc-bus1 {
244 bus-id = <1>;
245 cfg-val = <0x00300020>;
246 enable-msk = <0x70ff>;
249 soc-bus2 {
250 bus-id = <2>;
251 cfg-val = <0x00300020>;
252 enable-msk = <0x70ff>;
255 soc-bus3 {
256 bus-id = <3>;
257 cfg-val = <0x00300020>;
258 enable-msk = <0x70ff>;
261 soc-bus4 {
262 bus-id = <4>;
263 cfg-val = <0x00300020>;
264 enable-msk = <0x7011>;
267 soc-bus5 {
268 bus-id = <5>;
269 cfg-val = <0x00300020>;
270 enable-msk = <0x7011>;
273 soc-bus6 {
274 bus-id = <6>;
275 cfg-val = <0x00300020>;
276 enable-msk = <0x7011>;
279 soc-bus7 {
280 bus-id = <7>;
281 cfg-val = <0x00300020>;
282 enable-msk = <0x0>;
285 soc-bus8 {
286 bus-id = <8>;
287 cfg-val = <0x00300020>;
288 enable-msk = <0x0>;
291 soc-bus9 {
292 bus-id = <9>;
293 cfg-val = <0x00300020>;
294 enable-msk = <0x0>;
297 soc-bus10 {
298 bus-id = <10>;
299 cfg-val = <0x00300020>;
300 enable-msk = <0x0>;
303 soc-bus11 {
304 bus-id = <11>;
305 cfg-val = <0x00300020>;
306 enable-msk = <0x7000>;
311 display_subsystem: display-subsystem {
312 compatible = "rockchip,display-subsystem";
315 logo-memory-region = <&drm_logo>;
318 route_dsi: route-dsi {
327 route_rgb: route-rgb {
338 fiq_debugger: fiq-debugger {
339 compatible = "rockchip,fiq-debugger";
340 rockchip,serial-id = <2>;
341 rockchip,wake-irq = <0>;
342 rockchip,irq-mode-enable = <0>;
350 compatible = "linaro,optee-tz";
356 mipi_csi2: mipi-csi2 {
357 compatible = "rockchip,rv1126-mipi-csi2";
362 mpp_srv: mpp-srv {
363 compatible = "rockchip,mpp-service";
364 rockchip,taskqueue-count = <4>;
365 rockchip,resetgroup-count = <4>;
370 compatible = "arm,psci-1.0";
374 reserved-memory {
375 #address-cells = <1>;
376 #size-cells = <1>;
380 compatible = "shared-dma-pool";
384 linux,cma-default;
387 drm_logo: drm-logo@00000000 {
388 compatible = "rockchip,drm-logo";
393 compatible = "shared-dma-pool";
402 record-size = <0x20000>;
403 console-size = <0x40000>;
404 ftrace-size = <0x00000>;
405 pmsg-size = <0x40000>;
411 compatible = "rockchip,rkcif-dvp";
414 memory-region = <&isp_reserved>;
419 compatible = "rockchip,rkcif-sditf";
425 compatible = "rockchip,rkcif-mipi-lvds";
432 compatible = "rockchip,rkcif-sditf";
438 compatible = "rockchip,rkcif-mipi-lvds";
441 memory-region = <&isp_reserved>;
446 compatible = "rockchip,rkcif-sditf";
451 rockchip_suspend: rockchip-suspend {
452 compatible = "rockchip,pm-rv1126";
454 rockchip,sleep-debug-en = <0>;
455 rockchip,sleep-mode-config = <
463 rockchip,wakeup-config = <
470 rockchip_system_monitor: rockchip-system-monitor {
471 compatible = "rockchip,system-monitor";
474 thermal_zones: thermal-zones {
475 cpu_thermal: cpu-thermal {
476 polling-delay-passive = <20>; /* milliseconds */
477 polling-delay = <1000>; /* milliseconds */
478 sustainable-power = <875>; /* milliwatts */
483 thermal-sensors = <&cpu_tsadc 0>;
486 threshold: trip-point-0 {
493 target: trip-point-1 {
500 soc_crit: soc-crit {
509 cooling-maps {
512 cooling-device =
518 cooling-device =
524 cooling-device =
531 npu_thermal: npu-thermal {
532 polling-delay-passive = <20>; /* milliseconds */
533 polling-delay = <1000>; /* milliseconds */
534 sustainable-power = <977>; /* milliwatts */
536 thermal-sensors = <&npu_tsadc 0>;
541 compatible = "arm,armv7-timer";
546 clock-frequency = <24000000>;
550 compatible = "fixed-clock";
551 clock-frequency = <24000000>;
552 clock-output-names = "xin24m";
553 #clock-cells = <0>;
557 compatible = "fixed-clock";
558 clock-frequency = <0>;
559 clock-output-names = "dummy_cpll";
560 #clock-cells = <0>;
563 gmac_clkin_m0: external-gmac-clockm0 {
564 compatible = "fixed-clock";
565 clock-frequency = <125000000>;
566 clock-output-names = "clk_gmac_rgmii_clkin_m0";
567 #clock-cells = <0>;
570 gmac_clkini_m1: external-gmac-clockm1 {
571 compatible = "fixed-clock";
572 clock-frequency = <125000000>;
573 clock-output-names = "clk_gmac_rgmii_clkin_m1";
574 #clock-cells = <0>;
578 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
582 compatible = "rockchip,rv1126-rgb";
586 #address-cells = <1>;
587 #size-cells = <0>;
591 #address-cells = <1>;
592 #size-cells = <0>;
596 remote-endpoint = <&vop_out_rgb>;
605 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
608 pmu_io_domains: io-domains {
609 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
612 reboot-mode {
613 compatible = "syscon-reboot-mode";
615 mode-bootloader = <BOOT_BL_DOWNLOAD>;
616 mode-charge = <BOOT_CHARGING>;
617 mode-fastboot = <BOOT_FASTBOOT>;
618 mode-loader = <BOOT_BL_DOWNLOAD>;
619 mode-normal = <BOOT_NORMAL>;
620 mode-recovery = <BOOT_RECOVERY>;
621 mode-ums = <BOOT_UMS>;
622 mode-panic = <BOOT_PANIC>;
623 mode-watchdog = <BOOT_WATCHDOG>;
737 gic: interrupt-controller@feff0000 {
738 compatible = "arm,gic-400";
739 interrupt-controller;
740 #interrupt-cells = <3>;
741 #address-cells = <0>;
750 arm-debug@ff010000 {
759 compatible = "rockchip,rv1126-cpu-pvtm";
761 #address-cells = <1>;
762 #size-cells = <0>;
767 clock-names = "clk", "pclk";
769 reset-names = "rst", "rst-p";
773 pmu: power-management@ff3e0000 {
774 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
777 power: power-controller {
778 compatible = "rockchip,rv1126-power-controller";
779 #power-domain-cells = <1>;
780 #address-cells = <1>;
781 #size-cells = <0>;
898 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
901 #address-cells = <1>;
902 #size-cells = <0>;
904 clock-names = "i2c", "pclk";
905 pinctrl-names = "default";
906 pinctrl-0 = <&i2c0_xfer>;
911 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
914 #address-cells = <1>;
915 #size-cells = <0>;
918 clock-names = "i2c", "pclk";
919 pinctrl-names = "default";
920 pinctrl-0 = <&i2c2_xfer>;
925 compatible = "simple-bus";
926 #address-cells = <1>;
927 #size-cells = <1>;
930 dmac: dma-controller@ff4e0000 {
935 #dma-cells = <1>;
937 clock-names = "apb_pclk";
938 arm,pl330-periph-burst;
943 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
946 reg-shift = <2>;
947 reg-io-width = <4>;
949 clock-frequency = <24000000>;
951 clock-names = "baudclk", "apb_pclk";
952 pinctrl-names = "default";
953 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
958 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
960 #pwm-cells = <3>;
961 pinctrl-names = "active";
962 pinctrl-0 = <&pwm0m0_pins>;
964 clock-names = "pwm", "pclk";
969 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
971 #pwm-cells = <3>;
972 pinctrl-names = "active";
973 pinctrl-0 = <&pwm1m0_pins>;
975 clock-names = "pwm", "pclk";
980 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
982 #pwm-cells = <3>;
983 pinctrl-names = "active";
984 pinctrl-0 = <&pwm2m0_pins>;
986 clock-names = "pwm", "pclk";
991 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
993 #pwm-cells = <3>;
994 pinctrl-names = "active";
995 pinctrl-0 = <&pwm3m0_pins>;
997 clock-names = "pwm", "pclk";
1002 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1004 #pwm-cells = <3>;
1005 pinctrl-names = "active";
1006 pinctrl-0 = <&pwm4m0_pins>;
1008 clock-names = "pwm", "pclk";
1013 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1015 #pwm-cells = <3>;
1016 pinctrl-names = "active";
1017 pinctrl-0 = <&pwm5m0_pins>;
1019 clock-names = "pwm", "pclk";
1024 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1026 #pwm-cells = <3>;
1027 pinctrl-names = "active";
1028 pinctrl-0 = <&pwm6m0_pins>;
1030 clock-names = "pwm", "pclk";
1035 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1037 #pwm-cells = <3>;
1038 pinctrl-names = "active";
1039 pinctrl-0 = <&pwm7m0_pins>;
1041 clock-names = "pwm", "pclk";
1046 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1052 clock-names = "spiclk", "apb_pclk";
1054 dma-names = "tx", "rx";
1055 pinctrl-names = "default", "high_speed";
1056 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1057 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
1062 compatible = "rockchip,rv1126-pmu-pvtm";
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1070 clock-names = "clk", "pclk";
1073 reset-names = "rst", "rst-p";
1077 pmucru: clock-controller@ff480000 {
1078 compatible = "rockchip,rv1126-pmucru";
1081 #clock-cells = <1>;
1082 #reset-cells = <1>;
1085 cru: clock-controller@ff490000 {
1086 compatible = "rockchip,rv1126-cru";
1089 #clock-cells = <1>;
1090 #reset-cells = <1>;
1092 assigned-clocks =
1100 assigned-clock-rates =
1108 assigned-clock-parents =
1112 csi_dphy0: csi-dphy@ff4b0000 {
1113 compatible = "rockchip,rv1126-csi-dphy";
1116 clock-names = "pclk";
1121 csi_dphy1: csi-dphy@ff4b8000 {
1122 compatible = "rockchip,rv1126-csi-dphy";
1125 clock-names = "pclk";
1130 u2phy0: usb2-phy@ff4c0000 {
1131 compatible = "rockchip,rv1126-usb2phy";
1135 clock-names = "phyclk", "pclk";
1137 reset-names = "u2phy", "u2phy-apb";
1138 #clock-cells = <0>;
1141 u2phy_otg: otg-port {
1142 #phy-cells = <0>;
1147 interrupt-names = "otg-bvalid", "otg-id",
1153 u2phy1: usb2-phy@ff4c8000 {
1154 compatible = "rockchip,rv1126-usb2phy";
1158 clock-names = "phyclk", "pclk";
1159 assigned-clocks = <&cru USB480M>;
1160 assigned-clock-parents = <&u2phy1>;
1162 reset-names = "u2phy", "u2phy-apb";
1163 #clock-cells = <0>;
1164 clock-output-names = "usb480m_phy";
1167 u2phy_host: host-port {
1168 #phy-cells = <0>;
1171 interrupt-names = "linestate", "disconnect";
1176 mipi_dphy: mipi-dphy@ff4d0000 {
1177 compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk3568-video-phy";
1179 reg-names = "phy", "host";
1180 assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
1181 assigned-clock-rates = <24000000>;
1184 clock-names = "ref", "pclk", "pclk_host";
1185 #clock-cells = <0>;
1187 reset-names = "apb";
1188 #phy-cells = <0>;
1194 compatible = "rockchip,cryptov2-rng";
1197 clock-names = "hclk_crypto";
1198 power-domains = <&power RV1126_PD_CRYPTO>;
1200 reset-names = "reset";
1205 compatible = "rockchip,rv1126-crypto";
1210 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
1211 power-domains = <&power RV1126_PD_CRYPTO>;
1213 reset-names = "crypto-rst";
1218 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1224 clock-names = "i2c", "pclk";
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&i2c1_xfer>;
1231 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1237 clock-names = "i2c", "pclk";
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&i2c3m0_xfer>;
1244 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1250 clock-names = "i2c", "pclk";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&i2c4m0_xfer>;
1257 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1263 clock-names = "i2c", "pclk";
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&i2c5m0_xfer>;
1270 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1272 #pwm-cells = <3>;
1273 pinctrl-names = "active";
1274 pinctrl-0 = <&pwm8m0_pins>;
1276 clock-names = "pwm", "pclk";
1281 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1283 #pwm-cells = <3>;
1284 pinctrl-names = "active";
1285 pinctrl-0 = <&pwm9m0_pins>;
1287 clock-names = "pwm", "pclk";
1292 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1294 #pwm-cells = <3>;
1295 pinctrl-names = "active";
1296 pinctrl-0 = <&pwm10m0_pins>;
1298 clock-names = "pwm", "pclk";
1303 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1305 #pwm-cells = <3>;
1306 pinctrl-names = "active";
1307 pinctrl-0 = <&pwm11m0_pins>;
1309 clock-names = "pwm", "pclk";
1314 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1317 reg-shift = <2>;
1318 reg-io-width = <4>;
1320 clock-frequency = <24000000>;
1322 clock-names = "baudclk", "apb_pclk";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
1329 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1332 reg-shift = <2>;
1333 reg-io-width = <4>;
1335 clock-frequency = <24000000>;
1337 clock-names = "baudclk", "apb_pclk";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&uart2m1_xfer>;
1344 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1347 reg-shift = <2>;
1348 reg-io-width = <4>;
1350 clock-frequency = <24000000>;
1352 clock-names = "baudclk", "apb_pclk";
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>;
1359 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1362 reg-shift = <2>;
1363 reg-io-width = <4>;
1365 clock-frequency = <24000000>;
1367 clock-names = "baudclk", "apb_pclk";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
1374 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1377 reg-shift = <2>;
1378 reg-io-width = <4>;
1380 clock-frequency = <24000000>;
1382 clock-names = "baudclk", "apb_pclk";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
1389 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi";
1392 #address-cells = <1>;
1393 #size-cells = <0>;
1395 clock-names = "spiclk", "apb_pclk";
1397 dma-names = "tx", "rx";
1398 pinctrl-names = "default", "high_speed";
1399 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1400 pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
1405 compatible = "rockchip,rv1126-otp";
1407 #address-cells = <1>;
1408 #size-cells = <1>;
1410 clock-names = "otp", "apb_pclk";
1414 otp_cpu_code: cpu-code@2 {
1420 cpu_leakage: cpu-leakage@17 {
1423 logic_leakage: logic-leakage@18 {
1426 npu_leakage: npu-leakage@19 {
1429 venc_leakage: venc-leakage@1a {
1432 cpu_performance: cpu-performance@1e {
1436 npu_performance: npu-performance@1f {
1440 venc_performance: venc-performance@1f {
1444 cpu_tsadc_trim_l: cpu-tsadc-trim-l@23 {
1447 cpu_tsadc_trim_h: cpu-tsadc-trim-h@24 {
1451 npu_tsadc_trim_l: npu-tsadc-trim-l@25 {
1454 npu_tsadc_trim_h: npu-tsadc-trim-h@26 {
1458 tsadc_trim_base: tsadc-trim-base@27 {
1464 compatible = "rockchip,rk3399-saradc";
1467 #io-channel-cells = <1>;
1469 clock-names = "saradc", "apb_pclk";
1471 reset-names = "saradc-apb";
1476 compatible = "rockchip,rv1126-tsadc";
1480 assigned-clocks = <&cru CLK_CPU_TSADC>;
1481 assigned-clock-rates = <4000000>;
1484 clock-names = "tsadc", "apb_pclk", "phy_clk";
1487 reset-names = "tsadc-apb", "tsadc", "tsadc-phy";
1488 rockchip,hw-tshut-temp = <120000>;
1489 #thermal-sensor-cells = <1>;
1490 nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>, <&tsadc_trim_base>;
1491 nvmem-cell-names = "trim_l", "trim_h", "trim_base";
1492 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1493 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1494 pinctrl-names = "gpio", "otpout";
1495 pinctrl-0 = <&tsadcm0_shut>;
1496 pinctrl-1 = <&tsadc_shutorg>;
1501 compatible = "rockchip,rv1126-tsadc";
1505 assigned-clocks = <&cru CLK_NPU_TSADC>;
1506 assigned-clock-rates = <4000000>;
1509 clock-names = "tsadc", "apb_pclk", "phy_clk";
1512 reset-names = "tsadc-apb", "tsadc", "tsadc-phy";
1513 rockchip,hw-tshut-temp = <120000>;
1514 #thermal-sensor-cells = <1>;
1515 nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>, <&tsadc_trim_base>;
1516 nvmem-cell-names = "trim_l", "trim_h", "trim_base";
1517 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1518 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1519 pinctrl-names = "gpio", "otpout";
1520 pinctrl-0 = <&tsadcm0_shut>;
1521 pinctrl-1 = <&tsadc_shutorg>;
1532 compatible = "rockchip,can-1.0";
1535 assigned-clocks = <&cru CLK_CAN>;
1536 assigned-clock-rates = <200000000>;
1538 clock-names = "baudclk", "apb_pclk";
1540 reset-names = "can", "can-apb";
1545 compatible = "rockchip,rk3288-timer";
1549 clock-names = "pclk", "timer";
1553 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt";
1561 compatible = "rockchip,rv1126-mailbox",
1562 "rockchip,rk3368-mailbox";
1566 clock-names = "pclk_mailbox";
1567 #mbox-cells = <1>;
1572 compatible = "rockchip,hw-decompress";
1576 clock-names = "aclk", "dclk", "pclk";
1578 reset-names = "dresetn";
1583 compatible = "rockchip,rv1126-i2s-tdm";
1587 clock-names = "mclk_tx", "mclk_rx", "hclk";
1589 dma-names = "tx", "rx";
1591 reset-names = "tx-m", "rx-m";
1594 pinctrl-names = "default";
1595 pinctrl-0 = <&i2s0m0_sclk_tx
1608 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s";
1612 clock-names = "i2s_clk", "i2s_hclk";
1614 dma-names = "tx", "rx";
1615 pinctrl-names = "default";
1616 pinctrl-0 = <&i2s1m0_sclk
1624 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s";
1628 clock-names = "i2s_clk", "i2s_hclk";
1630 dma-names = "tx", "rx";
1631 pinctrl-names = "default";
1632 pinctrl-0 = <&i2s2m0_sclk
1640 compatible = "rockchip,rv1126-pdm", "rockchip,pdm";
1643 clock-names = "pdm_clk", "pdm_hclk";
1645 dma-names = "rx";
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&pdmm0_clk
1657 compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1";
1660 clock-names = "clk", "hclk";
1662 dma-names = "tx";
1663 pinctrl-names = "default";
1664 pinctrl-0 = <&audpwmm0_pins>;
1665 rockchip,sample-width-bits = <11>;
1666 rockchip,interpolat-points = <1>;
1670 rkacdc_dig: codec-digital@ff850000 {
1671 compatible = "rockchip,rv1126-codec-digital", "rockchip,codec-digital-v1";
1674 clock-names = "adc", "dac", "pclk";
1675 pinctrl-names = "default";
1676 pinctrl-0 = <&acodec_pins>;
1678 reset-names = "reset" ;
1685 compatible = "rockchip,rv1126-dfi";
1691 compatible = "rockchip,rv1126-dmc";
1694 interrupt-names = "complete";
1695 devfreq-events = <&dfi>;
1697 clock-names = "dmc_clk";
1698 operating-points-v2 = <&dmc_opp_table>;
1702 system-status-freq = <
1712 auto-min-freq = <328000>;
1713 auto-freq-en = <1>;
1714 #cooling-cells = <2>;
1718 dmc_opp_table: dmc-opp-table {
1719 compatible = "operating-points-v2";
1721 opp-328000000 {
1722 opp-hz = /bits/ 64 <328000000>;
1723 opp-microvolt = <800000>;
1725 opp-528000000 {
1726 opp-hz = /bits/ 64 <528000000>;
1727 opp-microvolt = <800000>;
1729 opp-784000000 {
1730 opp-hz = /bits/ 64 <784000000>;
1731 opp-microvolt = <800000>;
1733 opp-924000000 {
1734 opp-hz = /bits/ 64 <924000000>;
1735 opp-microvolt = <800000>;
1737 opp-1056000000 {
1738 opp-hz = /bits/ 64 <1056000000>;
1739 opp-microvolt = <800000>;
1745 compatible = "rockchip,rv1126-dmcdbg";
1750 compatible = "rockchip,rv1126-cif";
1752 reg-names = "cif_regs";
1754 interrupt-names = "cif-intr";
1757 clock-names = "aclk_cif","hclk_cif",
1762 reset-names = "rst_cif_a", "rst_cif_h",
1765 assigned-clocks = <&cru DCLK_CIF>;
1766 assigned-clock-rates = <300000000>;
1767 power-domains = <&power RV1126_PD_VI>;
1770 memory-region = <&isp_reserved>;
1778 interrupt-names = "cif_mmu";
1780 clock-names = "aclk", "iface";
1781 power-domains = <&power RV1126_PD_VI>;
1782 #iommu-cells = <0>;
1787 compatible = "rockchip,rv1126-cif-lite";
1789 reg-names = "cif_regs";
1791 interrupt-names = "cif-lite-intr";
1794 clock-names = "aclk_cif_lite","hclk_cif_lite",
1798 reset-names = "rst_cif_lite_a", "rst_cif_lite_h",
1800 assigned-clocks = <&cru DCLK_CIFLITE>;
1801 assigned-clock-rates = <300000000>;
1802 power-domains = <&power RV1126_PD_VI>;
1811 interrupt-names = "cif_lite_mmu";
1813 clock-names = "aclk", "iface";
1814 power-domains = <&power RV1126_PD_VI>;
1815 #iommu-cells = <0>;
1824 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
1825 power-domains = <&power RV1126_PD_VO>;
1830 compatible = "rockchip,rv1126-vop";
1832 reg-names = "regs", "gamma_lut";
1836 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1838 power-domains = <&power RV1126_PD_VO>;
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1847 remote-endpoint = <&rgb_in_vop>;
1852 remote-endpoint = <&dsi_in_vop>;
1861 interrupt-names = "vop_mmu";
1863 clock-names = "aclk", "iface";
1864 #iommu-cells = <0>;
1865 rockchip,disable-device-link-resume;
1866 power-domains = <&power RV1126_PD_VO>;
1870 mipi_csi2_hw: mipi-csi2-hw@ffb10000 {
1871 compatible = "rockchip,rv1126-mipi-csi2-hw";
1873 reg-names = "csihost_regs";
1876 interrupt-names = "csi-intr1", "csi-intr2";
1878 clock-names = "pclk_csi2host";
1880 reset-names = "srst_csihost_p";
1881 power-domains = <&power RV1126_PD_VI>;
1886 compatible = "rockchip,rv1126-iep", "rockchip,iep-v2";
1890 clock-names = "aclk", "hclk", "sclk";
1893 reset-names = "rst_a", "rst_h", "rst_s";
1894 power-domains = <&power RV1126_PD_VO>;
1896 rockchip,taskqueue-node = <3>;
1897 rockchip,resetgroup-node = <3>;
1906 interrupt-names = "iep_mmu";
1908 clock-names = "aclk", "iface";
1909 #iommu-cells = <0>;
1910 power-domains = <&power RV1126_PD_VO>;
1911 //rockchip,disable-device-link-resume;
1916 compatible = "rockchip,rv1126-mipi-dsi";
1920 clock-names = "pclk", "hclk";
1922 reset-names = "apb";
1924 phy-names = "dphy";
1926 #address-cells = <1>;
1927 #size-cells = <0>;
1928 power-domains = <&power RV1126_PD_VO>;
1934 remote-endpoint = <&vop_out_dsi>;
1941 compatible = "rockchip,rv1126-rkisp";
1946 interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
1949 clock-names = "aclk_isp", "hclk_isp", "clk_isp";
1950 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1951 assigned-clock-rates = <500000000>, <250000000>;
1953 reset-names = "isp", "isp-rx-p";
1954 power-domains = <&power RV1126_PD_VI>;
1956 memory-region = <&isp_reserved>;
1964 interrupt-names = "isp_mmu";
1966 clock-names = "aclk", "iface";
1967 power-domains = <&power RV1126_PD_VI>;
1968 #iommu-cells = <0>;
1969 rockchip,disable-mmu-reset;
1973 rkisp_vir0: rkisp-vir0 {
1974 compatible = "rockchip,rv1126-rkisp-vir";
1979 #address-cells = <1>;
1980 #size-cells = <0>;
1984 #address-cells = <1>;
1985 #size-cells = <0>;
1989 remote-endpoint = <&ispp0_in>;
1995 rkisp_vir1: rkisp-vir1 {
1996 compatible = "rockchip,rv1126-rkisp-vir";
2001 #address-cells = <1>;
2002 #size-cells = <0>;
2006 #address-cells = <1>;
2007 #size-cells = <0>;
2011 remote-endpoint = <&ispp1_in>;
2017 rkisp_vir2: rkisp-vir2 {
2018 compatible = "rockchip,rv1126-rkisp-vir";
2023 #address-cells = <1>;
2024 #size-cells = <0>;
2028 #address-cells = <1>;
2029 #size-cells = <0>;
2033 remote-endpoint = <&ispp2_in>;
2040 compatible = "rockchip,rv1126-rkispp";
2044 interrupt-names = "ispp_irq", "fec_irq";
2047 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
2048 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
2050 assigned-clock-rates = <500000000>, <250000000>,
2052 power-domains = <&power RV1126_PD_ISPP>;
2054 rockchip,restart-monitor-en;
2064 interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1";
2066 clock-names = "aclk", "iface";
2067 power-domains = <&power RV1126_PD_ISPP>;
2068 #iommu-cells = <0>;
2069 rockchip,disable-mmu-reset;
2073 rkispp_vir0: rkispp-vir0 {
2074 compatible = "rockchip,rv1126-rkispp-vir";
2079 #address-cells = <1>;
2080 #size-cells = <0>;
2084 remote-endpoint = <&isp0_out>;
2089 rkispp_vir1: rkispp-vir1 {
2090 compatible = "rockchip,rv1126-rkispp-vir";
2095 #address-cells = <1>;
2096 #size-cells = <0>;
2100 remote-endpoint = <&isp1_out>;
2105 rkispp_vir2: rkispp-vir2 {
2106 compatible = "rockchip,rv1126-rkispp-vir";
2111 #address-cells = <1>;
2112 #size-cells = <0>;
2116 remote-endpoint = <&isp2_out>;
2122 compatible = "rockchip,rkv-decoder-v1";
2125 interrupt-names = "irq_dec";
2129 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
2134 reset-names = "video_a", "video_h", "video_cabac",
2136 power-domains = <&power RV1126_PD_VDPU>;
2139 rockchip,taskqueue-node = <0>;
2140 rockchip,resetgroup-node = <0>;
2148 interrupt-names = "rkvdec_mmu";
2150 clock-names = "aclk", "iface";
2151 power-domains = <&power RV1126_PD_VDPU>;
2152 #iommu-cells = <0>;
2157 compatible = "rockchip,vpu-encoder-v2";
2161 clock-names = "aclk_vcodec", "hclk_vcodec";
2162 rockchip,normal-rates = <400000000>, <0>;
2163 rockchip,advanced-rates = <500000000>, <0>;
2164 rockchip,default-max-load = <2088960>;
2166 reset-names = "shared_video_a", "shared_video_h";
2169 rockchip,taskqueue-node = <1>;
2170 rockchip,resetgroup-node = <1>;
2171 power-domains = <&power RV1126_PD_VDPU>;
2176 compatible = "rockchip,vpu-decoder-v2";
2179 interrupt-names = "irq_dec";
2181 clock-names = "aclk_vcodec", "hclk_vcodec";
2183 reset-names = "shared_video_a", "shared_video_h";
2185 power-domains = <&power RV1126_PD_VDPU>;
2187 rockchip,taskqueue-node = <1>;
2188 rockchip,resetgroup-node = <1>;
2196 interrupt-names = "vpu_mmu";
2197 clock-names = "aclk", "iface";
2199 power-domains = <&power RV1126_PD_VDPU>;
2200 #iommu-cells = <0>;
2205 compatible = "rockchip,rkv-encoder-v1";
2208 interrupt-names = "irq_enc";
2211 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
2212 rockchip,normal-rates = <297000000>, <0>, <396000000>;
2213 rockchip,advanced-rates = <297000000>, <0>, <594000000>;
2214 rockchip,default-max-load = <2088960>;
2217 reset-names = "video_a", "video_h", "video_core";
2218 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>;
2219 assigned-clock-rates = <297000000>, <396000000>;
2220 operating-points-v2 = <&rkvenc_opp_table>;
2221 dynamic-power-coefficient = <1418>;
2222 #cooling-cells = <2>;
2224 node-name = "rkvenc";
2226 rockchip,taskqueue-node = <2>;
2227 rockchip,resetgroup-node = <2>;
2228 power-domains = <&power RV1126_PD_VEPU>;
2232 rkvenc_opp_table: rkvenc-opp-table {
2233 compatible = "operating-points-v2";
2235 nvmem-cells = <&venc_leakage>, <&venc_performance>;
2236 nvmem-cell-names = "leakage", "performance";
2238 rockchip,temp-freq-table = <
2244 rockchip,bin-scaling-sel = <
2248 rockchip,bin-voltage-sel = <
2252 rockchip,evb-irdrop = <25000>;
2255 opp-297000000 {
2256 opp-hz = /bits/ 64 <297000000>;
2257 opp-microvolt = <725000 725000 1000000>;
2258 opp-microvolt-L0 = <750000 750000 1000000>;
2260 opp-396000000 {
2261 opp-hz = /bits/ 64 <396000000>;
2262 opp-microvolt = <725000 725000 1000000>;
2263 opp-microvolt-L0 = <775000 775000 1000000>;
2265 opp-500000000 {
2266 opp-hz = /bits/ 64 <500000000>;
2267 opp-microvolt = <750000 750000 1000000>;
2268 opp-microvolt-L0 = <800000 800000 1000000>;
2270 opp-594000000 {
2271 opp-hz = /bits/ 64 <594000000>;
2272 opp-microvolt = <825000 825000 1000000>;
2281 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
2283 clock-names = "aclk", "iface";
2284 rockchip,disable-mmu-reset;
2285 rockchip,enable-cmd-retry;
2286 #iommu-cells = <0>;
2287 power-domains = <&power RV1126_PD_VEPU>;
2292 compatible = "rockchip,rv1126-npu-pvtm";
2294 #address-cells = <1>;
2295 #size-cells = <0>;
2300 clock-names = "clk", "pclk";
2302 reset-names = "rts", "rst-p";
2307 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
2311 interrupt-names = "macirq", "eth_wake_irq";
2317 clock-names = "stmmaceth", "mac_clk_rx",
2322 reset-names = "stmmaceth";
2324 snps,mixed-burst;
2327 snps,axi-config = <&stmmac_axi_setup>;
2328 snps,mtl-rx-config = <&mtl_rx_setup>;
2329 snps,mtl-tx-config = <&mtl_tx_setup>;
2333 compatible = "snps,dwmac-mdio";
2334 #address-cells = <0x1>;
2335 #size-cells = <0x0>;
2338 stmmac_axi_setup: stmmac-axi-config {
2344 mtl_rx_setup: rx-queues-config {
2345 snps,rx-queues-to-use = <1>;
2349 mtl_tx_setup: tx-queues-config {
2350 snps,tx-queues-to-use = <1>;
2356 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
2361 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
2362 fifo-depth = <0x100>;
2363 max-frequency = <200000000>;
2364 pinctrl-names = "default";
2365 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
2366 power-domains = <&power RV1126_PD_NVM>;
2367 rockchip,use-v2-tuning;
2372 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
2377 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
2378 fifo-depth = <0x100>;
2379 max-frequency = <200000000>;
2380 pinctrl-names = "normal", "idle";
2381 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
2382 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
2387 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
2392 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
2393 fifo-depth = <0x100>;
2394 max-frequency = <200000000>;
2395 pinctrl-names = "default";
2396 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
2397 power-domains = <&power RV1126_PD_SDIO>;
2402 compatible = "rockchip,rk-nandc";
2407 clock-names = "clk_nandc", "hclk_nandc";
2408 pinctrl-names = "default";
2409 pinctrl-0 = <&flash_pins>;
2410 power-domains = <&power RV1126_PD_NVM>;
2419 clock-names = "clk_sfc", "hclk_sfc";
2420 pinctrl-names = "default";
2421 pinctrl-0 = <&fspi_pins>;
2422 assigned-clocks = <&cru SCLK_SFC>;
2423 assigned-clock-rates = <80000000>;
2424 power-domains = <&power RV1126_PD_NVM>;
2425 #address-cells = <1>;
2426 #size-cells = <0>;
2434 clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu";
2435 assigned-clocks = <&cru CLK_CORE_NPU>, <&cru ACLK_NPU>;
2436 assigned-clock-rates = <396000000>, <600000000>;
2437 operating-points-v2 = <&npu_opp_table>;
2438 dynamic-power-coefficient = <1343>;
2439 #cooling-cells = <2>;
2441 power-domains = <&power RV1126_PD_NPU>;
2445 npu_opp_table: npu-opp-table {
2446 compatible = "operating-points-v2";
2448 nvmem-cells = <&npu_leakage>, <&npu_performance>;
2449 nvmem-cell-names = "leakage", "performance";
2451 rockchip,temp-freq-table = <
2458 rockchip,bin-scaling-sel = <
2463 rockchip,bin-voltage-sel = <
2466 rockchip,pvtm-voltage-sel = <
2471 rockchip,pvtm-freq = <396000>;
2472 rockchip,pvtm-volt = <800000>;
2473 rockchip,pvtm-ch = <1 0>;
2474 rockchip,pvtm-sample-time = <1000>;
2475 rockchip,pvtm-number = <10>;
2476 rockchip,pvtm-error = <1000>;
2477 rockchip,pvtm-ref-temp = <37>;
2478 rockchip,pvtm-temp-prop = <(-29) 0>;
2479 rockchip,pvtm-thermal-zone = "npu-thermal";
2481 opp-200000000 {
2482 opp-hz = /bits/ 64 <200000000>;
2483 opp-microvolt = <750000 750000 1000000>;
2484 opp-microvolt-L0 = <775000 775000 1000000>;
2486 opp-300000000 {
2487 opp-hz = /bits/ 64 <300000000>;
2488 opp-microvolt = <750000 750000 1000000>;
2489 opp-microvolt-L0 = <775000 775000 1000000>;
2491 opp-396000000 {
2492 opp-hz = /bits/ 64 <396000000>;
2493 opp-microvolt = <750000 750000 1000000>;
2494 opp-microvolt-L0 = <775000 775000 1000000>;
2496 opp-500000000 {
2497 opp-hz = /bits/ 64 <500000000>;
2498 opp-microvolt = <750000 750000 1000000>;
2499 opp-microvolt-L0 = <775000 775000 1000000>;
2501 opp-600000000 {
2502 opp-hz = /bits/ 64 <600000000>;
2503 opp-microvolt = <750000 750000 1000000>;
2504 opp-microvolt-L0 = <775000 775000 1000000>;
2506 opp-700000000 {
2507 opp-hz = /bits/ 64 <700000000>;
2508 opp-microvolt = <800000 800000 1000000>;
2509 opp-microvolt-L1 = <800000 800000 1000000>;
2510 opp-microvolt-L2 = <775000 775000 1000000>;
2511 opp-microvolt-L3 = <750000 750000 1000000>;
2513 opp-800000000 {
2514 opp-hz = /bits/ 64 <800000000>;
2515 opp-microvolt = <850000 850000 1000000>;
2516 opp-microvolt-L1 = <850000 850000 1000000>;
2517 opp-microvolt-L2 = <825000 825000 1000000>;
2518 opp-microvolt-L3 = <800000 800000 1000000>;
2520 opp-934000000 {
2521 opp-hz = /bits/ 64 <934000000>;
2522 opp-microvolt = <950000 950000 1000000>;
2523 opp-microvolt-L1 = <950000 950000 1000000>;
2524 opp-microvolt-L2 = <925000 925000 1000000>;
2525 opp-microvolt-L3 = <900000 900000 1000000>;
2530 compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3";
2531 #address-cells = <1>;
2532 #size-cells = <1>;
2536 clock-names = "ref_clk", "bus_clk", "hclk";
2544 maximum-speed = "high-speed";
2546 phy-names = "usb2-phy";
2548 power-domains = <&power RV1126_PD_USB>;
2550 reset-names = "usb3-otg";
2552 snps,dis-u2-freeclk-exists-quirk;
2554 snps,dis-del-phy-power-chg-quirk;
2555 snps,tx-ipgap-linecheck-dis-quirk;
2556 snps,tx-fifo-resize;
2557 snps,xhci-trb-ent-quirk;
2558 snps,usb2-lpm-disable;
2564 compatible = "generic-ehci";
2569 clock-names = "usbhost", "arbiter", "utmi";
2571 phy-names = "usb";
2572 power-domains = <&power RV1126_PD_USB>;
2577 compatible = "generic-ohci";
2582 clock-names = "usbhost", "arbiter", "utmi";
2584 phy-names = "usb";
2585 power-domains = <&power RV1126_PD_USB>;
2590 compatible = "rockchip,rv1126-pinctrl";
2593 #address-cells = <1>;
2594 #size-cells = <1>;
2598 compatible = "rockchip,gpio-bank";
2603 gpio-controller;
2604 #gpio-cells = <2>;
2606 interrupt-controller;
2607 #interrupt-cells = <2>;
2611 compatible = "rockchip,gpio-bank";
2616 gpio-controller;
2617 #gpio-cells = <2>;
2619 interrupt-controller;
2620 #interrupt-cells = <2>;
2624 compatible = "rockchip,gpio-bank";
2629 gpio-controller;
2630 #gpio-cells = <2>;
2632 interrupt-controller;
2633 #interrupt-cells = <2>;
2637 compatible = "rockchip,gpio-bank";
2642 gpio-controller;
2643 #gpio-cells = <2>;
2645 interrupt-controller;
2646 #interrupt-cells = <2>;
2650 compatible = "rockchip,gpio-bank";
2655 gpio-controller;
2656 #gpio-cells = <2>;
2658 interrupt-controller;
2659 #interrupt-cells = <2>;
2664 #include "rv1126-pinctrl.dtsi"