Lines Matching full:cru
6 #include <dt-bindings/clock/rv1126-cru.h>
57 clocks = <&cru ARMCLK>;
69 clocks = <&cru ARMCLK>;
80 clocks = <&cru ARMCLK>;
91 clocks = <&cru ARMCLK>;
125 clocks = <&cru PLL_APLL>;
766 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
768 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
787 clocks = <&cru ACLK_NPU>,
788 <&cru HCLK_NPU>,
789 <&cru PCLK_PDNPU>,
790 <&cru CLK_CORE_NPU>;
796 clocks = <&cru ACLK_VENC>,
797 <&cru HCLK_VENC>,
798 <&cru CLK_VENC_CORE>;
806 clocks = <&cru ACLK_CRYPTO>,
807 <&cru HCLK_CRYPTO>,
808 <&cru CLK_CRYPTO_CORE>,
809 <&cru CLK_CRYPTO_PKA>;
814 clocks = <&cru ACLK_ISP>,
815 <&cru HCLK_ISP>,
816 <&cru CLK_ISP>,
817 <&cru ACLK_CIF>,
818 <&cru HCLK_CIF>,
819 <&cru DCLK_CIF>,
820 <&cru CLK_CIF_OUT>,
821 <&cru CLK_MIPICSI_OUT>,
822 <&cru PCLK_CSIHOST>,
823 <&cru ACLK_CIFLITE>,
824 <&cru HCLK_CIFLITE>,
825 <&cru DCLK_CIFLITE>;
832 clocks = <&cru ACLK_RGA>,
833 <&cru HCLK_RGA>,
834 <&cru CLK_RGA_CORE>,
835 <&cru ACLK_VOP>,
836 <&cru HCLK_VOP>,
837 <&cru DCLK_VOP>,
838 <&cru PCLK_DSIHOST>,
839 <&cru ACLK_IEP>,
840 <&cru HCLK_IEP>,
841 <&cru CLK_IEP_CORE>;
847 clocks = <&cru ACLK_ISPP>,
848 <&cru HCLK_ISPP>,
849 <&cru CLK_ISPP>;
855 clocks = <&cru ACLK_VDEC>,
856 <&cru HCLK_VDEC>,
857 <&cru CLK_VDEC_CORE>,
858 <&cru CLK_VDEC_CA>,
859 <&cru CLK_VDEC_HEVC_CA>,
860 <&cru ACLK_JPEG>,
861 <&cru HCLK_JPEG>;
867 clocks = <&cru HCLK_EMMC>,
868 <&cru CLK_EMMC>,
869 <&cru HCLK_NANDC>,
870 <&cru CLK_NANDC>,
871 <&cru HCLK_SFC>,
872 <&cru HCLK_SFCXIP>,
873 <&cru SCLK_SFC>;
880 clocks = <&cru HCLK_SDIO>,
881 <&cru CLK_SDIO>;
886 clocks = <&cru HCLK_USBHOST>,
887 <&cru HCLK_USBHOST_ARB>,
888 <&cru CLK_USBHOST_UTMI_OHCI>,
889 <&cru ACLK_USBOTG>,
890 <&cru CLK_USBOTG_REF>;
936 clocks = <&cru ACLK_DMAC>;
1085 cru: clock-controller@ff490000 { label
1086 compatible = "rockchip,rv1126-cru";
1094 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
1095 <&cru PLL_HPLL>, <&cru ARMCLK>,
1096 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
1097 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
1098 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
1099 <&cru HCLK_PDCORE_NIU>;
1115 clocks = <&cru PCLK_CSIPHY0>;
1124 clocks = <&cru PCLK_CSIPHY1>;
1134 clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>;
1136 resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>;
1157 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
1159 assigned-clocks = <&cru USB480M>;
1161 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>;
1183 <&cru PCLK_DSIPHY>, <&cru PCLK_DSIHOST>;
1186 resets = <&cru SRST_DSIPHY_P>;
1196 clocks = <&cru HCLK_CRYPTO>;
1199 resets = <&cru SRST_CRYPTO_CORE>;
1208 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>,
1209 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
1212 resets = <&cru SRST_CRYPTO_CORE>;
1223 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1236 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1249 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1262 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1275 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1286 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1297 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1308 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1321 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
1336 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1351 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1366 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1381 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1394 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1409 clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>;
1468 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1470 resets = <&cru SRST_SARADC_P>;
1480 assigned-clocks = <&cru CLK_CPU_TSADC>;
1482 clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>,
1483 <&cru CLK_CPU_TSADCPHY>;
1485 resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>,
1486 <&cru SRST_CPU_TSADCPHY>;
1492 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1505 assigned-clocks = <&cru CLK_NPU_TSADC>;
1507 clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>,
1508 <&cru CLK_NPU_TSADCPHY>;
1510 resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>,
1511 <&cru SRST_NPU_TSADCPHY>;
1517 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1535 assigned-clocks = <&cru CLK_CAN>;
1537 clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>;
1539 resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>;
1548 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
1555 clocks = <&cru PCLK_WDT>;
1565 clocks = <&cru PCLK_MAILBOX>;
1575 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
1577 resets = <&cru SRST_DECOM_D>;
1586 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>;
1590 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>;
1592 rockchip,cru = <&cru>;
1611 clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>;
1627 clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>;
1642 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1659 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
1673 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, <&cru PCLK_ACDCDIG>;
1677 resets = <&cru SRST_ACDCDIG>;
1696 clocks = <&cru SCLK_DDRCLK>;
1755 clocks = <&cru ACLK_CIF>,<&cru HCLK_CIF>,
1756 <&cru DCLK_CIF>;
1759 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
1760 <&cru SRST_CIF_D>, <&cru SRST_CIF_P>,
1761 <&cru SRST_CIF_I>, <&cru SRST_CIF_RX_P>;
1765 assigned-clocks = <&cru DCLK_CIF>;
1779 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
1792 clocks = <&cru ACLK_CIFLITE>,<&cru HCLK_CIFLITE>,
1793 <&cru DCLK_CIFLITE>;
1796 resets = <&cru SRST_CIFLITE_A>, <&cru SRST_CIFLITE_H>,
1797 <&cru SRST_CIFLITE_D>, <&cru SRST_CIFLITE_RX_P>;
1800 assigned-clocks = <&cru DCLK_CIFLITE>;
1812 clocks = <&cru ACLK_CIFLITE>, <&cru HCLK_CIFLITE>;
1823 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
1835 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1862 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1877 clocks = <&cru PCLK_CSIHOST>;
1879 resets = <&cru SRST_CSIHOST_P>;
1889 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
1891 resets = <&cru SRST_IEP_A>, <&cru SRST_IEP_H>,
1892 <&cru SRST_IEP_CORE>;
1907 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1919 clocks = <&cru PCLK_DSIHOST>, <&cru HCLK_PDVO>;
1921 resets = <&cru SRST_DSIHOST_P>;
1947 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1948 <&cru CLK_ISP>;
1950 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1952 resets = <&cru SRST_ISP>, <&cru SRST_ISP_RX_P>;
1965 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
2045 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
2046 <&cru CLK_ISPP>;
2048 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
2049 <&cru CLK_ISPP>;
2065 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>;
2126 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>,
2127 <&cru CLK_VDEC_CA>, <&cru CLK_VDEC_CORE>,
2128 <&cru CLK_VDEC_HEVC_CA>;
2131 resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>,
2132 <&cru SRST_VDEC_CA>, <&cru SRST_VDEC_CORE>,
2133 <&cru SRST_VDEC_HEVC_CA>;
2149 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>;
2160 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>;
2165 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>;
2180 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>;
2182 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>;
2198 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>;
2209 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>,
2210 <&cru CLK_VENC_CORE>;
2215 resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>,
2216 <&cru SRST_VENC_CORE>;
2218 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>;
2282 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>;
2299 clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>;
2301 resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>;
2313 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
2314 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
2315 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
2316 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
2321 resets = <&cru SRST_GMAC_A>;
2359 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
2360 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
2375 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
2376 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
2390 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
2391 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
2406 clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>;
2418 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
2422 assigned-clocks = <&cru SCLK_SFC>;
2433 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, <&cru PCLK_PDNPU>, <&cru CLK_CORE_NPU>;
2435 assigned-clocks = <&cru CLK_CORE_NPU>, <&cru ACLK_NPU>;
2534 clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>,
2535 <&cru HCLK_PDUSB>;
2549 resets = <&cru SRST_USBOTG_A>;
2567 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
2580 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
2614 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2627 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2640 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2653 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;