Lines Matching +full:0 +full:xffb80000
50 #size-cells = <0>;
55 reg = <0xf00>;
67 reg = <0xf01>;
78 reg = <0xf02>;
89 reg = <0xf03>;
103 arm,psci-suspend-param = <0x0010000>;
127 0 5
131 1 0
134 0 100500 1
141 rockchip,pvtm-ch = <0 0>;
238 bus-id = <0>;
239 cfg-val = <0x00300020>;
240 enable-msk = <0x7144>;
245 cfg-val = <0x00300020>;
246 enable-msk = <0x70ff>;
251 cfg-val = <0x00300020>;
252 enable-msk = <0x70ff>;
257 cfg-val = <0x00300020>;
258 enable-msk = <0x70ff>;
263 cfg-val = <0x00300020>;
264 enable-msk = <0x7011>;
269 cfg-val = <0x00300020>;
270 enable-msk = <0x7011>;
275 cfg-val = <0x00300020>;
276 enable-msk = <0x7011>;
281 cfg-val = <0x00300020>;
282 enable-msk = <0x0>;
287 cfg-val = <0x00300020>;
288 enable-msk = <0x0>;
293 cfg-val = <0x00300020>;
294 enable-msk = <0x0>;
299 cfg-val = <0x00300020>;
300 enable-msk = <0x0>;
305 cfg-val = <0x00300020>;
306 enable-msk = <0x7000>;
341 rockchip,wake-irq = <0>;
342 rockchip,irq-mode-enable = <0>;
383 size = <0x800000>;
389 reg = <0x0 0x0>;
396 size = <0x10000000>;
401 reg = <0x8000000 0x100000>;
402 record-size = <0x20000>;
403 console-size = <0x40000>;
404 ftrace-size = <0x00000>;
405 pmsg-size = <0x40000>;
454 rockchip,sleep-debug-en = <0>;
456 (0
464 (0
481 k_i = <0>;
483 thermal-sensors = <&cpu_tsadc 0>;
486 threshold: trip-point-0 {
536 thermal-sensors = <&npu_tsadc 0>;
553 #clock-cells = <0>;
558 clock-frequency = <0>;
560 #clock-cells = <0>;
567 #clock-cells = <0>;
574 #clock-cells = <0>;
579 reg = <0xfe000000 0x20000>;
587 #size-cells = <0>;
589 port@0 {
590 reg = <0>;
592 #size-cells = <0>;
594 rgb_in_vop: endpoint@0 {
595 reg = <0>;
606 reg = <0xfe020000 0x1000>;
614 offset = <0x200>;
629 reg = <0xfe810000 0x20>;
634 reg = <0xfe810080 0x20>;
639 reg = <0xfe850000 0x20>;
644 reg = <0xfe860000 0x20>;
649 reg = <0xfe860080 0x20>;
654 reg = <0xfe860200 0x20>;
659 reg = <0xfe86c000 0x20>;
664 reg = <0xfe870000 0x20>;
669 reg = <0xfe870080 0x20>;
674 reg = <0xfe870100 0x20>;
679 reg = <0xfe880000 0x20>;
684 reg = <0xfe880080 0x20>;
689 reg = <0xfe890000 0x20>;
694 reg = <0xfe890080 0x20>;
699 reg = <0xfe890100 0x20>;
704 reg = <0xfe8a0000 0x20>;
709 reg = <0xfe8a0080 0x20>;
714 reg = <0xfe8a0100 0x20>;
719 reg = <0xfe8a0180 0x20>;
724 reg = <0xfe8b0000 0x20>;
729 reg = <0xfe8c0000 0x20>;
734 reg = <0xfe8d0000 0x20>;
741 #address-cells = <0>;
743 reg = <0xfeff1000 0x1000>,
744 <0xfeff2000 0x2000>,
745 <0xfeff4000 0x2000>,
746 <0xfeff6000 0x2000>;
752 reg = <0xff010000 0x1000>,
753 <0xff012000 0x1000>,
754 <0xff014000 0x1000>,
755 <0xff016000 0x1000>;
760 reg = <0xff040000 0x100>;
762 #size-cells = <0>;
764 pvtm@0 {
765 reg = <0>;
775 reg = <0xff3e0000 0x1000>;
781 #size-cells = <0>;
899 reg = <0xff3f0000 0x1000>;
902 #size-cells = <0>;
906 pinctrl-0 = <&i2c0_xfer>;
912 reg = <0xff400000 0x1000>;
915 #size-cells = <0>;
920 pinctrl-0 = <&i2c2_xfer>;
932 reg = <0xff4e0000 0x4000>;
944 reg = <0xff410000 0x100>;
953 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
959 reg = <0xff430000 0x10>;
962 pinctrl-0 = <&pwm0m0_pins>;
970 reg = <0xff430010 0x10>;
973 pinctrl-0 = <&pwm1m0_pins>;
981 reg = <0xff430020 0x10>;
984 pinctrl-0 = <&pwm2m0_pins>;
992 reg = <0xff430030 0x10>;
995 pinctrl-0 = <&pwm3m0_pins>;
1003 reg = <0xff440000 0x10>;
1006 pinctrl-0 = <&pwm4m0_pins>;
1014 reg = <0xff440010 0x10>;
1017 pinctrl-0 = <&pwm5m0_pins>;
1025 reg = <0xff440020 0x10>;
1028 pinctrl-0 = <&pwm6m0_pins>;
1036 reg = <0xff440030 0x10>;
1039 pinctrl-0 = <&pwm7m0_pins>;
1047 reg = <0xff450000 0x1000>;
1050 #size-cells = <0>;
1053 dmas = <&dmac 1>, <&dmac 0>;
1056 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1063 reg = <0xff470000 0x100>;
1065 #size-cells = <0>;
1079 reg = <0xff480000 0x1000>;
1087 reg = <0xff490000 0x1000>;
1114 reg = <0xff4b0000 0x8000>;
1123 reg = <0xff4b8000 0x8000>;
1132 reg = <0xff4c0000 0x8000>;
1138 #clock-cells = <0>;
1142 #phy-cells = <0>;
1155 reg = <0xff4c8000 0x8000>;
1163 #clock-cells = <0>;
1168 #phy-cells = <0>;
1178 reg = <0xff4d0000 0x500>, <0xffb30000 0x500>;
1185 #clock-cells = <0>;
1188 #phy-cells = <0>;
1195 reg = <0xff500400 0x80>;
1206 reg = <0xff500000 0x400>, <0xff500480 0x3B80>;
1219 reg = <0xff510000 0x1000>;
1222 #size-cells = <0>;
1226 pinctrl-0 = <&i2c1_xfer>;
1232 reg = <0xff520000 0x1000>;
1235 #size-cells = <0>;
1239 pinctrl-0 = <&i2c3m0_xfer>;
1245 reg = <0xff530000 0x1000>;
1248 #size-cells = <0>;
1252 pinctrl-0 = <&i2c4m0_xfer>;
1258 reg = <0xff540000 0x1000>;
1261 #size-cells = <0>;
1265 pinctrl-0 = <&i2c5m0_xfer>;
1271 reg = <0xff550000 0x10>;
1274 pinctrl-0 = <&pwm8m0_pins>;
1282 reg = <0xff550010 0x10>;
1285 pinctrl-0 = <&pwm9m0_pins>;
1293 reg = <0xff550020 0x10>;
1296 pinctrl-0 = <&pwm10m0_pins>;
1304 reg = <0xff550030 0x10>;
1307 pinctrl-0 = <&pwm11m0_pins>;
1315 reg = <0xff560000 0x100>;
1324 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
1330 reg = <0xff570000 0x100>;
1339 pinctrl-0 = <&uart2m1_xfer>;
1345 reg = <0xff580000 0x100>;
1354 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>;
1360 reg = <0xff590000 0x100>;
1369 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
1375 reg = <0xff5a0000 0x100>;
1384 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
1390 reg = <0xff5b0000 0x1000>;
1393 #size-cells = <0>;
1399 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1406 reg = <0xff5c0000 0x1000>;
1415 reg = <0x02 0x2>;
1418 reg = <0x07 0x10>;
1421 reg = <0x17 0x1>;
1424 reg = <0x18 0x1>;
1427 reg = <0x19 0x1>;
1430 reg = <0x1a 0x1>;
1433 reg = <0x1e 0x1>;
1437 reg = <0x1f 0x1>;
1438 bits = <0 2>;
1441 reg = <0x1f 0x1>;
1445 reg = <0x23 0x1>;
1448 reg = <0x24 0x1>;
1449 bits = <0 4>;
1452 reg = <0x25 0x1>;
1455 reg = <0x26 0x1>;
1456 bits = <0 4>;
1459 reg = <0x27 0x1>;
1465 reg = <0xff5e0000 0x100>;
1477 reg = <0xff5f0000 0x100>;
1492 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1493 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1495 pinctrl-0 = <&tsadcm0_shut>;
1502 reg = <0xff5f8000 0x100>;
1517 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1518 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1520 pinctrl-0 = <&tsadcm0_shut>;
1527 reg = <0xff600000 0x1000>;
1533 reg = <0xff610000 0x100>;
1546 reg = <0xff660000 0x20>;
1554 reg = <0xff680000 0x100>;
1563 reg = <0xff6a0000 0x1000>;
1573 reg = <0xff6c0000 0x1000>;
1584 reg = <0xff800000 0x1000>;
1595 pinctrl-0 = <&i2s0m0_sclk_tx
1609 reg = <0xff810000 0x1000>;
1616 pinctrl-0 = <&i2s1m0_sclk
1625 reg = <0xff820000 0x1000>;
1632 pinctrl-0 = <&i2s2m0_sclk
1641 reg = <0xff830000 0x1000>;
1647 pinctrl-0 = <&pdmm0_clk
1658 reg = <0xff840000 0x1000>;
1664 pinctrl-0 = <&audpwmm0_pins>;
1672 reg = <0xff850000 0x1000>;
1676 pinctrl-0 = <&acodec_pins>;
1684 reg = <0xff9c0000 0x400>;
1693 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1751 reg = <0xffae0000 0x8000>;
1776 reg = <0xffae0800 0x100>;
1782 #iommu-cells = <0>;
1788 reg = <0xffae8000 0x8000>;
1809 reg = <0xffae8800 0x100>;
1815 #iommu-cells = <0>;
1821 reg = <0xffaf0000 0x1000>;
1831 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
1843 #size-cells = <0>;
1845 vop_out_rgb: endpoint@0 {
1846 reg = <0>;
1859 reg = <0xffb00f00 0x100>;
1864 #iommu-cells = <0>;
1872 reg = <0xffb10000 0x10000>;
1887 reg = <0xffb20000 0x500>;
1904 reg = <0xffb20800 0x100>;
1909 #iommu-cells = <0>;
1917 reg = <0xffb30000 0x500>;
1927 #size-cells = <0>;
1942 reg = <0xffb50000 0x10000>;
1962 reg = <0xffb51a00 0x100>;
1968 #iommu-cells = <0>;
1980 #size-cells = <0>;
1985 #size-cells = <0>;
2002 #size-cells = <0>;
2007 #size-cells = <0>;
2024 #size-cells = <0>;
2029 #size-cells = <0>;
2041 reg = <0xffb60000 0x20000>;
2060 reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>;
2068 #iommu-cells = <0>;
2080 #size-cells = <0>;
2082 ispp0_in: endpoint@0 {
2083 reg = <0>;
2096 #size-cells = <0>;
2098 ispp1_in: endpoint@0 {
2099 reg = <0>;
2112 #size-cells = <0>;
2114 ispp2_in: endpoint@0 {
2115 reg = <0>;
2123 reg = <0xffb80000 0x400>;
2139 rockchip,taskqueue-node = <0>;
2140 rockchip,resetgroup-node = <0>;
2146 reg = <0xffb80480 0x40>, <0xffb804c0 0x40>;
2152 #iommu-cells = <0>;
2158 reg = <0xffb90000 0x400>;
2162 rockchip,normal-rates = <400000000>, <0>;
2163 rockchip,advanced-rates = <500000000>, <0>;
2177 reg = <0xffb90400 0x400>;
2194 reg = <0xffb90800 0x40>;
2200 #iommu-cells = <0>;
2206 reg = <0xffbb0000 0x400>;
2212 rockchip,normal-rates = <297000000>, <0>, <396000000>;
2213 rockchip,advanced-rates = <297000000>, <0>, <594000000>;
2245 0 37
2249 1 0
2278 reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>;
2286 #iommu-cells = <0>;
2293 reg = <0xffc00000 0x100>;
2295 #size-cells = <0>;
2308 reg = <0xffc40000 0x0ffff>;
2334 #address-cells = <0x1>;
2335 #size-cells = <0x0>;
2341 snps,blen = <0 0 0 0 16 8 4>;
2357 reg = <0xffc50000 0x4000>;
2362 fifo-depth = <0x100>;
2365 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
2373 reg = <0xffc60000 0x4000>;
2378 fifo-depth = <0x100>;
2381 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
2388 reg = <0xffc70000 0x4000>;
2393 fifo-depth = <0x100>;
2396 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
2403 reg = <0xffc80000 0x4000>;
2405 nandc_id = <0>;
2409 pinctrl-0 = <&flash_pins>;
2416 reg = <0xffc90000 0x4000>;
2421 pinctrl-0 = <&fspi_pins>;
2426 #size-cells = <0>;
2432 reg = <0xffbc0000 0x4000>;
2459 0 23
2464 2 0
2467 0 108500 1
2473 rockchip,pvtm-ch = <1 0>;
2478 rockchip,pvtm-temp-prop = <(-29) 0>;
2541 reg = <0xffd00000 0x100000>;
2565 reg = <0xffe00000 0x10000>;
2578 reg = <0xffe10000 0x10000>;
2599 reg = <0xff460000 0x100>;
2612 reg = <0xff620000 0x100>;
2625 reg = <0xff630000 0x100>;
2638 reg = <0xff640000 0x100>;
2651 reg = <0xff650000 0x100>;