Lines Matching +full:pwm +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include <dt-bindings/clock/rv1106-cru.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/soc/rockchip-system-status.h>
12 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 interrupt-parent = <&gic>;
66 compatible = "simple-bus";
68 cpu_pvtpll: cpu-pvtpll {
69 compatible = "fixed-clock";
70 clock-frequency = <1300000000>;
71 clock-output-names = "cpu_pvtpll";
72 #clock-cells = <0>;
76 rkvenc_pvtpll: pvtpll-0 {
77 compatible = "fixed-clock";
78 clock-frequency = <410000000>;
79 clock-output-names = "clk_pvtpll_0";
80 #clock-cells = <0>;
83 npu_pvtpll: pvtpll-1 {
84 compatible = "fixed-clock";
85 clock-frequency = <420000000>;
86 clock-output-names = "clk_pvtpll_1";
87 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <24000000>;
93 clock-output-names = "xin24m";
94 #clock-cells = <0>;
99 #address-cells = <1>;
100 #size-cells = <0>;
104 compatible = "arm,cortex-a7";
107 operating-points-v2 = <&cpu0_opp_table>;
111 cpu0_opp_table: cpu0-opp-table {
112 compatible = "operating-points-v2";
113 opp-shared;
115 nvmem-cells = <&cpu_leakage>;
116 nvmem-cell-names = "leakage";
118 rockchip,pvtpll-avg-offset = <0x4001c>;
119 rockchip,pvtpll-min-rate = <1104000>;
120 rockchip,pvtpll-volt-step = <12500>;
122 rockchip,temp-hysteresis = <5000>;
123 rockchip,low-temp = <10000>;
124 rockchip,low-temp-min-volt = <900000>;
126 opp-408000000 {
127 opp-hz = /bits/ 64 <408000000>;
128 opp-microvolt = <850000 850000 1000000>;
129 clock-latency-ns = <40000>;
131 opp-600000000 {
132 opp-hz = /bits/ 64 <600000000>;
133 opp-microvolt = <850000 850000 1000000>;
134 clock-latency-ns = <40000>;
136 opp-816000000 {
137 opp-hz = /bits/ 64 <816000000>;
138 opp-microvolt = <850000 850000 1000000>;
139 clock-latency-ns = <40000>;
140 opp-suspend;
142 opp-1104000000 {
143 opp-hz = /bits/ 64 <1104000000>;
144 opp-microvolt = <850000 850000 1000000>;
145 clock-latency-ns = <40000>;
147 opp-1200000000 {
148 opp-hz = /bits/ 64 <1200000000>;
149 opp-microvolt = <850000 850000 1000000>;
150 clock-latency-ns = <40000>;
152 opp-1296000000 {
153 opp-hz = /bits/ 64 <1296000000>;
154 opp-microvolt = <875000 850000 1000000>;
155 clock-latency-ns = <40000>;
157 opp-1416000000 {
158 opp-hz = /bits/ 64 <1416000000>;
159 opp-microvolt = <925000 850000 1000000>;
160 clock-latency-ns = <40000>;
162 opp-1512000000 {
163 opp-hz = /bits/ 64 <1512000000>;
164 opp-microvolt = <975000 850000 1000000>;
165 clock-latency-ns = <40000>;
167 opp-1608000000 {
168 opp-hz = /bits/ 64 <1608000000>;
169 opp-microvolt = <1000000 850000 1000000>;
170 clock-latency-ns = <40000>;
174 arm-pmu {
175 compatible = "arm,cortex-a7-pmu";
177 interrupt-affinity = <&cpu0>;
182 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
183 nvmem-cell-names = "id", "cpu-version", "cpu-code";
187 csi2_dphy0: csi2-dphy0 {
188 compatible = "rockchip,rv1106-csi2-dphy";
194 csi2_dphy1: csi2-dphy1 {
195 compatible = "rockchip,rv1106-csi2-dphy";
201 csi2_dphy2: csi2-dphy2 {
202 compatible = "rockchip,rv1106-csi2-dphy";
207 display_subsystem: display-subsystem {
208 compatible = "rockchip,display-subsystem";
213 route_rgb: route-rgb {
224 fiq_debugger: fiq-debugger {
225 compatible = "rockchip,fiq-debugger";
226 rockchip,serial-id = <2>;
227 rockchip,wake-irq = <0>;
228 rockchip,irq-mode-enable = <0>;
236 compatible = "linaro,optee-tz";
242 mipi0_csi2: mipi0-csi2 {
243 compatible = "rockchip,rv1106-mipi-csi2";
248 mipi1_csi2: mipi1-csi2 {
249 compatible = "rockchip,rv1106-mipi-csi2";
254 mpp_srv: mpp-srv {
255 compatible = "rockchip,mpp-service";
256 rockchip,taskqueue-count = <2>;
260 mpp_vcodec: mpp-vcodec {
266 compatible = "arm,psci-1.0";
270 rkcif_dvp: rkcif-dvp {
271 compatible = "rockchip,rkcif-dvp";
276 rkcif_dvp_sditf: rkcif-dvp-sditf {
277 compatible = "rockchip,rkcif-sditf";
282 rkcif_mipi_lvds: rkcif-mipi-lvds {
283 compatible = "rockchip,rkcif-mipi-lvds";
288 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
289 compatible = "rockchip,rkcif-sditf";
294 rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
295 compatible = "rockchip,rkcif-mipi-lvds";
300 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
301 compatible = "rockchip,rkcif-sditf";
306 rkisp_vir0: rkisp-vir0 {
307 compatible = "rockchip,rkisp-vir";
313 rkisp_vir1: rkisp-vir1 {
314 compatible = "rockchip,rkisp-vir";
319 rkisp_vir2: rkisp-vir2 {
320 compatible = "rockchip,rkisp-vir";
325 rkisp_vir3: rkisp-vir3 {
326 compatible = "rockchip,rkisp-vir";
331 rockchip_system_monitor: rockchip-system-monitor {
332 compatible = "rockchip,system-monitor";
334 rockchip,thermal-zone = "soc-thermal";
337 thermal_zones: thermal-zones {
338 soc_thermal: soc-thermal {
339 polling-delay-passive = <20>; /* milliseconds */
340 polling-delay = <1000>; /* milliseconds */
341 sustainable-power = <2100>; /* milliwatts */
343 thermal-sensors = <&tsadc 0>;
345 threshold: trip-point-0 {
350 target: trip-point-1 {
355 soc_crit: soc-crit {
367 compatible = "arm,armv7-timer";
370 clock-frequency = <24000000>;
374 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd";
377 grf_cru: grf-clock-controller {
378 compatible = "rockchip,rv1106-grf-cru";
379 #clock-cells = <1>;
382 reboot_mode: reboot-mode {
383 compatible = "syscon-reboot-mode";
385 mode-bootloader = <BOOT_BL_DOWNLOAD>;
386 mode-charge = <BOOT_CHARGING>;
387 mode-fastboot = <BOOT_FASTBOOT>;
388 mode-loader = <BOOT_BL_DOWNLOAD>;
389 mode-normal = <BOOT_NORMAL>;
390 mode-recovery = <BOOT_RECOVERY>;
391 mode-ums = <BOOT_UMS>;
392 mode-panic = <BOOT_PANIC>;
393 mode-watchdog = <BOOT_WATCHDOG>;
397 compatible = "rockchip,rv1106-rgb";
401 #address-cells = <1>;
402 #size-cells = <0>;
406 #address-cells = <1>;
407 #size-cells = <0>;
411 remote-endpoint = <&vop_out_rgb>;
417 rknpor_powergood: rknpor-powergood {
418 compatible = "rockchip,rv1106-npor-powergood";
425 compatible = "rockchip,rv1106-rtc";
430 clock-names = "pclk_phy", "pclk_test";
431 assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
432 assigned-clock-rates = <24000000>;
436 gic: interrupt-controller@ff1f0000 {
437 compatible = "arm,gic-400";
438 interrupt-controller;
439 #interrupt-cells = <3>;
440 #address-cells = <0>;
449 arm-debug@ff200000 {
455 compatible = "rockchip,rv1106-core-pvtm";
457 #address-cells = <1>;
458 #size-cells = <0>;
463 clock-names = "clk";
465 reset-names = "rst", "rst-p";
469 pmu: power-management@ff300000 {
470 compatible = "rockchip,rv1106-pmu", "syscon";
475 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
478 #address-cells = <1>;
479 #size-cells = <0>;
481 clock-names = "i2c", "pclk";
482 pinctrl-names = "default";
483 pinctrl-0 = <&i2c0m0_xfer>;
488 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
491 #address-cells = <1>;
492 #size-cells = <0>;
494 clock-names = "i2c", "pclk";
495 pinctrl-names = "default";
496 pinctrl-0 = <&i2c1m0_xfer>;
500 dsm: codec-digital@ff340000 {
501 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1";
504 clock-names = "dac", "pclk";
506 reset-names = "reset" ;
508 rockchip,pwm-output-mode;
509 #sound-dai-cells = <0>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&dsmaudio_pins>;
515 pwm0: pwm@ff350000 {
516 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
519 #pwm-cells = <3>;
520 pinctrl-names = "active";
521 pinctrl-0 = <&pwm0m0_pins>;
523 clock-names = "pwm", "pclk";
527 pwm1: pwm@ff350010 {
528 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
531 #pwm-cells = <3>;
532 pinctrl-names = "active";
533 pinctrl-0 = <&pwm1m0_pins>;
535 clock-names = "pwm", "pclk";
539 pwm2: pwm@ff350020 {
540 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
543 #pwm-cells = <3>;
544 pinctrl-names = "active";
545 pinctrl-0 = <&pwm2m0_pins>;
547 clock-names = "pwm", "pclk";
551 pwm3: pwm@ff350030 {
552 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
556 #pwm-cells = <3>;
557 pinctrl-names = "active";
558 pinctrl-0 = <&pwm3m0_pins>;
560 clock-names = "pwm", "pclk";
564 pwm4: pwm@ff360000 {
565 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
568 #pwm-cells = <3>;
569 pinctrl-names = "active";
570 pinctrl-0 = <&pwm4m0_pins>;
572 clock-names = "pwm", "pclk";
576 pwm5: pwm@ff360010 {
577 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
580 #pwm-cells = <3>;
581 pinctrl-names = "active";
582 pinctrl-0 = <&pwm5m0_pins>;
584 clock-names = "pwm", "pclk";
588 pwm6: pwm@ff360020 {
589 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
592 #pwm-cells = <3>;
593 pinctrl-names = "active";
594 pinctrl-0 = <&pwm6m0_pins>;
596 clock-names = "pwm", "pclk";
600 pwm7: pwm@ff360030 {
601 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
605 #pwm-cells = <3>;
606 pinctrl-names = "active";
607 pinctrl-0 = <&pwm7m0_pins>;
609 clock-names = "pwm", "pclk";
614 compatible = "rockchip,rv1106-mailbox",
615 "rockchip,rk3368-mailbox";
619 clock-names = "pclk_mailbox";
620 #mbox-cells = <1>;
625 compatible = "rockchip,rv1106-pmuioc", "syscon";
630 compatible = "rockchip,rv1106-pmu-pvtm";
632 #address-cells = <1>;
633 #size-cells = <0>;
638 clock-names = "clk", "pclk";
640 reset-names = "rst", "rst-p";
644 cru: clock-controller@ff3a0000 {
645 compatible = "rockchip,rv1106-cru";
648 #clock-cells = <1>;
649 #reset-cells = <1>;
651 assigned-clocks =
658 assigned-clock-rates =
668 compatible = "rockchip,rv1106-saradc";
671 #io-channel-cells = <1>;
673 clock-names = "saradc", "apb_pclk";
675 reset-names = "saradc-apb";
680 compatible = "rockchip,rv1106-tsadc";
685 clock-names = "tsadc", "apb_pclk", "tsen";
686 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
687 assigned-clock-rates = <1000000>, <12000000>;
689 reset-names = "tsadc", "tsadc-apb";
690 #thermal-sensor-cells = <1>;
691 rockchip,hw-tshut-temp = <120000>;
692 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
693 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
698 compatible = "rockchip,rv1106-otp";
700 #address-cells = <1>;
701 #size-cells = <1>;
705 clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
709 reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
712 cpu_code: cpu-code@2 {
715 otp_cpu_version: cpu-version@8 {
722 cpu_leakage: cpu-leakage@1a {
725 log_leakage: log-leakage@1b {
728 macphy_bgs: macphy-bgs@2d {
731 macphy_txlevel: macphy-txlevel@2e {
736 u2phy: usb2-phy@ff3e0000 {
737 compatible = "rockchip,rv1106-usb2phy";
741 clock-names = "phyclk", "pclk";
743 reset-names = "u2phy", "u2phy-apb";
744 #clock-cells = <0>;
747 u2phy_otg: otg-port {
748 #phy-cells = <0>;
753 interrupt-names = "otg-bvalid", "otg-id",
759 csi2_dphy_hw: csi2-dphy-hw@ff3e8000 {
760 compatible = "rockchip,rv1106-csi2-dphy-hw";
763 clock-names = "pclk";
765 reset-names = "srst_p_csiphy";
770 dmac: dma-controller@ff420000 {
782 #dma-cells = <1>;
784 clock-names = "apb_pclk";
785 arm,pl330-periph-burst;
789 compatible = "rockchip,crypto-v3";
794 clock-names = "aclk", "hclk", "sclk", "pka";
795 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
796 assigned-clock-rates = <200000000>, <200000000>;
798 reset-names = "crypto-rst";
807 clock-names = "hclk_trng";
809 reset-names = "reset";
814 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
817 #address-cells = <1>;
818 #size-cells = <0>;
820 clock-names = "i2c", "pclk";
821 pinctrl-names = "default";
822 pinctrl-0 = <&i2c2m0_xfer>;
827 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
830 #address-cells = <1>;
831 #size-cells = <0>;
833 clock-names = "i2c", "pclk";
834 pinctrl-names = "default";
835 pinctrl-0 = <&i2c3m0_xfer>;
840 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
843 #address-cells = <1>;
844 #size-cells = <0>;
846 clock-names = "i2c", "pclk";
847 pinctrl-names = "default";
848 pinctrl-0 = <&i2c4m0_xfer>;
853 compatible = "rockchip,rv1106-codec";
859 clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu";
861 reset-names = "acodec-reset";
863 init-mic-gain = <0x22>; /* Left:20dB Right:20dB */
867 pwm8: pwm@ff490000 {
868 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
871 #pwm-cells = <3>;
872 pinctrl-names = "active";
873 pinctrl-0 = <&pwm8m0_pins>;
875 clock-names = "pwm", "pclk";
879 pwm9: pwm@ff490010 {
880 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
883 #pwm-cells = <3>;
884 pinctrl-names = "active";
885 pinctrl-0 = <&pwm9m0_pins>;
887 clock-names = "pwm", "pclk";
891 pwm10: pwm@ff490020 {
892 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
895 #pwm-cells = <3>;
896 pinctrl-names = "active";
897 pinctrl-0 = <&pwm10m0_pins>;
899 clock-names = "pwm", "pclk";
903 pwm11: pwm@ff490030 {
904 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
908 #pwm-cells = <3>;
909 pinctrl-names = "active";
910 pinctrl-0 = <&pwm11m0_pins>;
912 clock-names = "pwm", "pclk";
917 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
920 reg-shift = <2>;
921 reg-io-width = <4>;
923 clock-frequency = <24000000>;
925 clock-names = "baudclk", "apb_pclk";
926 pinctrl-names = "default";
927 pinctrl-0 = <&uart0m0_xfer>;
932 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
935 reg-shift = <2>;
936 reg-io-width = <4>;
938 clock-frequency = <24000000>;
940 clock-names = "baudclk", "apb_pclk";
941 pinctrl-names = "default";
942 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
947 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
950 reg-shift = <2>;
951 reg-io-width = <4>;
953 clock-frequency = <24000000>;
955 clock-names = "baudclk", "apb_pclk";
956 pinctrl-names = "default";
957 pinctrl-0 = <&uart2m1_xfer>;
962 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
965 reg-shift = <2>;
966 reg-io-width = <4>;
968 clock-frequency = <24000000>;
970 clock-names = "baudclk", "apb_pclk";
971 pinctrl-names = "default";
972 pinctrl-0 = <&uart3m0_xfer>;
977 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
980 reg-shift = <2>;
981 reg-io-width = <4>;
983 clock-frequency = <24000000>;
985 clock-names = "baudclk", "apb_pclk";
986 pinctrl-names = "default";
987 pinctrl-0 = <&uart4m0_xfer>;
992 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
995 reg-shift = <2>;
996 reg-io-width = <4>;
998 clock-frequency = <24000000>;
1000 clock-names = "baudclk", "apb_pclk";
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
1007 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1013 clock-names = "spiclk", "apb_pclk", "sclk_in";
1015 dma-names = "tx", "rx";
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1022 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1028 clock-names = "spiclk", "apb_pclk";
1029 assigned-clocks = <&cru CLK_SPI1>;
1030 assigned-clock-rates = <200000000>;
1032 dma-names = "tx", "rx";
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1039 compatible = "rockchip,hw-decompress";
1043 clock-names = "aclk", "dclk", "pclk";
1045 reset-names = "dresetn";
1050 compatible = "rockchip,rv1106-ioc", "syscon";
1055 compatible = "rockchip,rv1106-wdt", "snps,dw-wdt";
1058 clock-names = "tclk", "pclk";
1064 compatible = "rockchip,rv1106-mailbox",
1065 "rockchip,rk3368-mailbox";
1069 clock-names = "pclk_mailbox";
1070 #mbox-cells = <1>;
1075 compatible = "rockchip,rv1106-rknpu";
1079 clock-names = "aclk", "hclk";
1080 assigned-clocks = <&cru ACLK_RKNN>;
1081 assigned-clock-rates = <420000000>;
1083 reset-names = "srst_a", "srst_h";
1088 compatible = "mmio-sram";
1090 #address-cells = <1>;
1091 #size-cells = <1>;
1093 rkisp_sram: rkisp-sram@0 {
1096 hpmcu_sram: hpmcu-sram@3f000 {
1106 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
1111 compatible = "rockchip,rv1106-vop";
1113 reg-names = "regs";
1117 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1126 remote-endpoint = <&rgb_in_vop>;
1132 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
1137 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1138 fifo-depth = <0x100>;
1139 max-frequency = <200000000>;
1144 compatible = "rockchip,rv1106-rkisp";
1149 interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
1152 clock-names = "aclk_isp", "hclk_isp",
1159 compatible = "rockchip,rv1106-cif";
1161 reg-names = "cif_regs";
1163 interrupt-names = "cif-intr";
1170 clock-names = "aclk_cif","hclk_cif",
1181 reset-names = "rst_cif_a","rst_cif_h",
1190 mipi0_csi2_hw: mipi-csi2-hw@ffa20000 {
1191 compatible = "rockchip,rv1106-mipi-csi2-hw";
1193 reg-names = "csihost_regs";
1196 interrupt-names = "csi-intr1", "csi-intr2";
1198 clock-names = "pclk_csi2host", "clk_rxbyte_hs";
1200 reset-names = "srst_csihost_p";
1204 mipi1_csi2_hw: mipi-csi2-hw@ffa30000 {
1205 compatible = "rockchip,rv1106-mipi-csi2-hw";
1207 reg-names = "csihost_regs";
1210 interrupt-names = "csi-intr1", "csi-intr2";
1212 clock-names = "pclk_csi2host", "clk_rxbyte_hs";
1214 reset-names = "srst_csihost_p";
1219 compatible = "rockchip,rkv-encoder-rv1106";
1222 interrupt-names = "irq_rkvenc";
1224 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1225 rockchip,normal-rates = <300000000>, <0>, <410000000>;
1226 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
1227 assigned-clock-rates = <300000000>, <400000000>;
1229 reset-names = "video_a", "video_h", "video_core";
1231 rockchip,taskqueue-node = <0>;
1236 rkvenc_pp: rkvenc-pp@ffa60000 {
1237 compatible = "rockchip,rkvenc-pp-rv1106";
1240 interrupt-names = "irq_rkvenc_pp";
1242 clock-names = "aclk_vepu_pp", "hclk_vepu_pp";
1243 assigned-clocks = <&cru ACLK_VEPU_PP>, <&cru HCLK_VEPU_PP>;
1246 rockchip,taskqueue-node = <1>;
1251 compatible = "rockchip,rk-dvbm";
1254 interrupt-names = "irq_rkdvbm";
1256 clock-names = "clk_core";
1257 assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>;
1258 assigned-clock-rates = <200000000>;
1260 reset-names = "dvbm_rst";
1265 compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a";
1269 interrupt-names = "macirq", "eth_wake_irq";
1273 clock-names = "stmmaceth", "clk_mac_ref",
1276 reset-names = "stmmaceth";
1278 snps,mixed-burst;
1281 tx-dma-size = <256>;
1282 rx-dma-size = <128>;
1284 snps,axi-config = <&stmmac_axi_setup>;
1285 snps,mtl-rx-config = <&mtl_rx_setup>;
1286 snps,mtl-tx-config = <&mtl_tx_setup>;
1288 phy-mode = "rmii";
1290 phy-handle = <&rmii_phy>;
1293 snps,flow-ctrl = <0>;
1295 nvmem-cells = <&macphy_bgs>;
1296 nvmem-cell-names = "bgs";
1300 compatible = "snps,dwmac-mdio";
1301 #address-cells = <0x1>;
1302 #size-cells = <0x0>;
1303 rmii_phy: ethernet-phy@2 {
1304 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
1308 phy-is-integrated;
1309 nvmem-cells = <&macphy_txlevel>;
1310 nvmem-cell-names = "txlevel";
1315 stmmac_axi_setup: stmmac-axi-config {
1321 mtl_rx_setup: rx-queues-config {
1322 snps,rx-queues-to-use = <1>;
1328 mtl_tx_setup: tx-queues-config {
1329 snps,tx-queues-to-use = <1>;
1337 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
1342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1343 fifo-depth = <0x100>;
1344 max-frequency = <200000000>;
1345 rockchip,use-v2-tuning;
1350 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
1355 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1356 fifo-depth = <0x100>;
1357 max-frequency = <200000000>;
1366 clock-names = "clk_sfc", "hclk_sfc";
1367 assigned-clocks = <&cru SCLK_SFC>;
1368 assigned-clock-rates = <75000000>;
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1379 clock-names = "aclk_rve", "hclk_rve";
1384 compatible = "rockchip,rv1106-i2s-tdm";
1388 clock-names = "mclk_tx", "mclk_rx", "hclk";
1390 dma-names = "tx", "rx";
1392 reset-names = "tx-m", "rx-m";
1393 rockchip,clk-trcm = <1>;
1394 #sound-dai-cells = <0>;
1399 compatible = "rockchip,rv1106-dwc3", "rockchip,rk3399-dwc3";
1402 clock-names = "ref", "utmi", "bus";
1403 #address-cells = <1>;
1404 #size-cells = <1>;
1413 reset-names = "usb3-otg";
1415 maximum-speed = "high-speed";
1417 phy-names = "usb2-phy";
1420 snps,dis-u2-freeclk-exists-quirk;
1422 snps,dis-del-phy-power-chg-quirk;
1423 snps,dis-tx-ipgap-linecheck-quirk;
1424 snps,usb2-gadget-lpm-disable;
1425 snps,usb2-lpm-disable;
1431 compatible = "rockchip,rv1106-pinctrl";
1434 #address-cells = <1>;
1435 #size-cells = <1>;
1439 compatible = "rockchip,gpio-bank";
1444 gpio-controller;
1445 #gpio-cells = <2>;
1446 gpio-ranges = <&pinctrl 0 0 32>;
1447 interrupt-controller;
1448 #interrupt-cells = <2>;
1452 compatible = "rockchip,gpio-bank";
1457 gpio-controller;
1458 #gpio-cells = <2>;
1459 gpio-ranges = <&pinctrl 0 32 32>;
1460 interrupt-controller;
1461 #interrupt-cells = <2>;
1465 compatible = "rockchip,gpio-bank";
1470 gpio-controller;
1471 #gpio-cells = <2>;
1472 gpio-ranges = <&pinctrl 0 64 32>;
1473 interrupt-controller;
1474 #interrupt-cells = <2>;
1478 compatible = "rockchip,gpio-bank";
1483 gpio-controller;
1484 #gpio-cells = <2>;
1485 gpio-ranges = <&pinctrl 0 96 32>;
1486 interrupt-controller;
1487 #interrupt-cells = <2>;
1491 compatible = "rockchip,gpio-bank";
1496 gpio-controller;
1497 #gpio-cells = <2>;
1498 gpio-ranges = <&pinctrl 0 128 32>;
1499 interrupt-controller;
1500 #interrupt-cells = <2>;
1505 #include "rv1106-pinctrl.dtsi"