Lines Matching full:cru
5 #include <dt-bindings/clock/rv1106-cru.h>
106 clocks = <&cru ARMCLK>;
378 compatible = "rockchip,rv1106-grf-cru";
429 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
431 assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
462 clocks = <&cru CLK_PVTM_CORE>;
464 resets = <&cru SRST_PVTM_CORE>, <&cru SRST_P_PVTM_CORE>;
480 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
493 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
503 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
505 resets = <&cru SRST_M_DSM>;
522 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
534 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
546 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
559 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
571 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
583 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
595 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
608 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
618 clocks = <&cru PCLK_PMU_MAILBOX>;
637 clocks = <&cru CLK_PVTM_PMU>, <&cru PCLK_PVTM_PMU>;
639 resets = <&cru SRST_PVTM_PMU>, <&cru SRST_P_PVTM_PMU>;
644 cru: clock-controller@ff3a0000 { label
645 compatible = "rockchip,rv1106-cru";
652 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
653 <&cru ARMCLK>,
654 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
655 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
656 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
657 <&cru HCLK_PMU_ROOT>;
672 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
674 resets = <&cru SRST_P_SARADC>;
684 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>;
686 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
688 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
692 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
702 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
703 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>,
704 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>;
706 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
707 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>,
708 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>;
740 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
742 resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>;
762 clocks = <&cru PCLK_MIPICSIPHY>;
764 resets = <&cru SRST_P_MIPICSIPHY>;
783 clocks = <&cru ACLK_DMAC>;
792 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
793 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
795 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
797 resets = <&cru SRST_CORE_CRYPTO>;
806 clocks = <&cru HCLK_TRNG_NS>;
808 resets = <&cru SRST_H_TRNG_NS>;
819 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
832 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
845 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
856 clocks = <&cru PCLK_ACODEC>,
857 <&cru MCLK_ACODEC_TX>,
858 <&cru MCLK_I2S0_8CH_TX>;
860 resets = <&cru SRST_P_ACODEC>;
874 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
886 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
898 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
911 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
924 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
939 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
954 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
969 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
984 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
999 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1012 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>;
1027 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1029 assigned-clocks = <&cru CLK_SPI1>;
1042 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
1044 resets = <&cru SRST_D_DECOM>;
1057 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1068 clocks = <&cru PCLK_MAILBOX>;
1078 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
1080 assigned-clocks = <&cru ACLK_RKNN>;
1082 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>;
1105 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
1116 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1135 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1150 clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
1151 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>;
1164 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
1165 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
1166 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
1167 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
1168 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>,
1169 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>;
1176 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
1177 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
1178 <&cru SRST_VICAP_I0>, <&cru SRST_VICAP_I1>,
1179 <&cru SRST_VICAP_RX0>, <&cru SRST_VICAP_RX1>,
1180 <&cru SRST_VICAP_ISP0>, <&cru SRST_P_VICAP_VEPU>;
1197 clocks = <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>;
1199 resets = <&cru SRST_P_CSIHOST0>;
1211 clocks = <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>;
1213 resets = <&cru SRST_P_CSIHOST1>;
1223 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>;
1226 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
1228 resets = <&cru SRST_A_VEPU>, <&cru SRST_H_VEPU>, <&cru SRST_CORE_VEPU>;
1241 clocks = <&cru ACLK_VEPU_PP>, <&cru HCLK_VEPU_PP>;
1243 assigned-clocks = <&cru ACLK_VEPU_PP>, <&cru HCLK_VEPU_PP>;
1244 resets = <&cru SRST_A_VEPU_PP>, <&cru SRST_H_VEPU_PP>;
1255 clocks = <&cru CLK_CORE_VEPU_DVBM>;
1257 assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>;
1259 resets = <&cru SRST_CORE_VEPU_DVBM>;
1271 clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>,
1272 <&cru ACLK_MAC>, <&cru PCLK_MAC>;
1275 resets = <&cru SRST_A_MAC>;
1306 clocks = <&cru CLK_MACPHY>;
1307 resets = <&cru SRST_MACPHY>;
1340 clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>,
1353 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>,
1365 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1367 assigned-clocks = <&cru SCLK_SFC>;
1378 clocks = <&cru ACLK_IVE>, <&cru HCLK_IVE>;
1387 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>;
1391 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1400 clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>,
1401 <&cru ACLK_USBOTG>;
1412 resets = <&cru SRST_A_USBOTG>;
1442 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
1455 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1468 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1481 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1494 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;