Lines Matching +full:0 +full:xffa30000
72 #clock-cells = <0>;
76 rkvenc_pvtpll: pvtpll-0 {
80 #clock-cells = <0>;
87 #clock-cells = <0>;
94 #clock-cells = <0>;
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0x0>;
118 rockchip,pvtpll-avg-offset = <0x4001c>;
227 rockchip,wake-irq = <0>;
228 rockchip,irq-mode-enable = <0>;
343 thermal-sensors = <&tsadc 0>;
345 threshold: trip-point-0 {
375 reg = <0xff000000 0x68000>;
384 offset = <0x20200>;
402 #size-cells = <0>;
404 port@0 {
405 reg = <0>;
407 #size-cells = <0>;
409 rgb_in_vop: endpoint@0 {
410 reg = <0>;
426 reg = <0xff1c0000 0x1000>;
440 #address-cells = <0>;
442 reg = <0xff1f1000 0x1000>,
443 <0xff1f2000 0x2000>,
444 <0xff1f4000 0x2000>,
445 <0xff1f6000 0x2000>;
451 reg = <0xff200000 0x1000>;
456 reg = <0xff240000 0x100>;
458 #size-cells = <0>;
460 pvtm@0 {
461 reg = <0>;
471 reg = <0xff300000 0x1000>;
476 reg = <0xff310000 0x1000>;
479 #size-cells = <0>;
483 pinctrl-0 = <&i2c0m0_xfer>;
489 reg = <0xff320000 0x1000>;
492 #size-cells = <0>;
496 pinctrl-0 = <&i2c1m0_xfer>;
502 reg = <0xff340000 0x1000>;
509 #sound-dai-cells = <0>;
511 pinctrl-0 = <&dsmaudio_pins>;
517 reg = <0xff350000 0x10>;
521 pinctrl-0 = <&pwm0m0_pins>;
529 reg = <0xff350010 0x10>;
533 pinctrl-0 = <&pwm1m0_pins>;
541 reg = <0xff350020 0x10>;
545 pinctrl-0 = <&pwm2m0_pins>;
553 reg = <0xff350030 0x10>;
558 pinctrl-0 = <&pwm3m0_pins>;
566 reg = <0xff360000 0x10>;
570 pinctrl-0 = <&pwm4m0_pins>;
578 reg = <0xff360010 0x10>;
582 pinctrl-0 = <&pwm5m0_pins>;
590 reg = <0xff360020 0x10>;
594 pinctrl-0 = <&pwm6m0_pins>;
602 reg = <0xff360030 0x10>;
607 pinctrl-0 = <&pwm7m0_pins>;
616 reg = <0xff378000 0x200>;
626 reg = <0xff388000 0x1000>;
631 reg = <0xff390000 0x100>;
633 #size-cells = <0>;
635 pvtm@0 {
646 reg = <0xff3a0000 0x20000>;
669 reg = <0xff3c0000 0x200>;
681 reg = <0xff3c8000 0x1000>;
692 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
693 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
699 reg = <0xff3d0000 0x4000>;
713 reg = <0x02 0x2>;
716 reg = <0x08 0x1>;
720 reg = <0x0a 0x10>;
723 reg = <0x1a 0x1>;
726 reg = <0x1b 0x1>;
729 reg = <0x2d 0x1>;
732 reg = <0x2e 0x2>;
738 reg = <0xff3e0000 0x8000>;
744 #clock-cells = <0>;
748 #phy-cells = <0>;
761 reg = <0xff3e8000 0x8000>;
772 reg = <0xff420000 0x4000>;
790 reg = <0xff440000 0x2000>;
804 reg = <0xff448000 0x200>;
815 reg = <0xff450000 0x1000>;
818 #size-cells = <0>;
822 pinctrl-0 = <&i2c2m0_xfer>;
828 reg = <0xff460000 0x1000>;
831 #size-cells = <0>;
835 pinctrl-0 = <&i2c3m0_xfer>;
841 reg = <0xff470000 0x1000>;
844 #size-cells = <0>;
848 pinctrl-0 = <&i2c4m0_xfer>;
854 reg = <0xff480000 0x1000>;
863 init-mic-gain = <0x22>; /* Left:20dB Right:20dB */
869 reg = <0xff490000 0x10>;
873 pinctrl-0 = <&pwm8m0_pins>;
881 reg = <0xff490010 0x10>;
885 pinctrl-0 = <&pwm9m0_pins>;
893 reg = <0xff490020 0x10>;
897 pinctrl-0 = <&pwm10m0_pins>;
905 reg = <0xff490030 0x10>;
910 pinctrl-0 = <&pwm11m0_pins>;
918 reg = <0xff4a0000 0x100>;
927 pinctrl-0 = <&uart0m0_xfer>;
933 reg = <0xff4b0000 0x100>;
942 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
948 reg = <0xff4c0000 0x100>;
957 pinctrl-0 = <&uart2m1_xfer>;
963 reg = <0xff4d0000 0x100>;
972 pinctrl-0 = <&uart3m0_xfer>;
978 reg = <0xff4e0000 0x100>;
987 pinctrl-0 = <&uart4m0_xfer>;
993 reg = <0xff4f0000 0x100>;
1002 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
1008 reg = <0xff500000 0x1000>;
1011 #size-cells = <0>;
1014 dmas = <&dmac 1>, <&dmac 0>;
1017 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1023 reg = <0xff510000 0x1000>;
1026 #size-cells = <0>;
1034 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1040 reg = <0xff520000 0x1000>;
1051 reg = <0xff538000 0x40000>;
1056 reg = <0xff5a0000 0x100>;
1066 reg = <0xff5c0000 0x200>;
1076 reg = <0xff660000 0x10000>;
1089 reg = <0xff6c0000 0x40000>;
1092 ranges = <0 0xff6c0000 0x40000>;
1093 rkisp_sram: rkisp-sram@0 {
1094 reg = <0x0 0x3f000>;
1097 reg = <0x3f000 0x1000>;
1103 reg = <0xff980000 0x1000>;
1112 reg = <0xff990000 0x200>;
1122 #size-cells = <0>;
1124 vop_out_rgb: endpoint@0 {
1125 reg = <0>;
1133 reg = <0xff9a0000 0x4000>;
1138 fifo-depth = <0x100>;
1145 reg = <0xffa00000 0x7f00>;
1160 reg = <0xffa10000 0x10000>;
1192 reg = <0xffa20000 0x10000>;
1206 reg = <0xffa30000 0x10000>;
1220 reg = <0xffa50000 0x6000>;
1225 rockchip,normal-rates = <300000000>, <0>, <410000000>;
1231 rockchip,taskqueue-node = <0>;
1238 reg = <0xffa60000 0x900>;
1252 reg = <0xffa70000 0x90>;
1266 reg = <0xffa80000 0x10000>;
1292 /* FLOW_OFF: 0, FLOW_RX: 1, FLOW_TX: 2, FLOW_AUTO: 3 */
1293 snps,flow-ctrl = <0>;
1301 #address-cells = <0x1>;
1302 #size-cells = <0x0>;
1318 snps,blen = <0 0 0 0 16 8 4>;
1338 reg = <0xffa90000 0x4000>;
1343 fifo-depth = <0x100>;
1351 reg = <0xffaa0000 0x4000>;
1356 fifo-depth = <0x100>;
1363 reg = <0xffac0000 0x4000>;
1370 #size-cells = <0>;
1376 reg = <0xffad0000 0x1000>;
1385 reg = <0xffae0000 0x1000>;
1394 #sound-dai-cells = <0>;
1410 reg = <0xffb00000 0x100000>;
1440 reg = <0xff380000 0x100>;
1446 gpio-ranges = <&pinctrl 0 0 32>;
1453 reg = <0xff530000 0x100>;
1459 gpio-ranges = <&pinctrl 0 32 32>;
1466 reg = <0xff540000 0x100>;
1472 gpio-ranges = <&pinctrl 0 64 32>;
1479 reg = <0xff550000 0x100>;
1485 gpio-ranges = <&pinctrl 0 96 32>;
1492 reg = <0xff560000 0x100>;
1498 gpio-ranges = <&pinctrl 0 128 32>;