Lines Matching +full:sclk +full:- +full:strength
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/suspend/rockchip-rk3288.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
19 interrupt-parent = <&gic>;
54 arm-pmu {
55 compatible = "arm,cortex-a12-pmu";
60 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 compatible = "arm,psci-1.0";
69 #address-cells = <1>;
70 #size-cells = <0>;
71 enable-method = "rockchip,rk3066-smp";
76 compatible = "arm,cortex-a12";
78 enable-method = "psci";
80 operating-points-v2 = <&cpu_opp_table>;
81 #cooling-cells = <2>; /* min followed by max */
82 clock-latency = <40000>;
84 dynamic-power-coefficient = <370>;
88 compatible = "arm,cortex-a12";
90 enable-method = "psci";
92 operating-points-v2 = <&cpu_opp_table>;
93 #cooling-cells = <2>; /* min followed by max */
94 clock-latency = <40000>;
96 dynamic-power-coefficient = <370>;
100 compatible = "arm,cortex-a12";
102 enable-method = "psci";
104 operating-points-v2 = <&cpu_opp_table>;
105 #cooling-cells = <2>; /* min followed by max */
106 clock-latency = <40000>;
108 dynamic-power-coefficient = <370>;
112 compatible = "arm,cortex-a12";
114 enable-method = "psci";
116 operating-points-v2 = <&cpu_opp_table>;
117 #cooling-cells = <2>; /* min followed by max */
118 clock-latency = <40000>;
120 dynamic-power-coefficient = <370>;
124 cpu_opp_table: cpu-opp-table {
125 compatible = "operating-points-v2";
126 opp-shared;
129 rockchip,avs-scale = <17>;
130 rockchip,max-volt = <1350000>;
131 nvmem-cells = <&cpu_leakage>, <&special_function>,
134 nvmem-cell-names = "leakage", "special",
136 "performance-w", "package";
137 rockchip,bin-scaling-sel = <
143 rockchip,pvtm-voltage-sel = <
149 rockchip,pvtm-freq = <408000>;
150 rockchip,pvtm-volt = <1000000>;
151 rockchip,pvtm-ch = <0 0>;
152 rockchip,pvtm-sample-time = <1000>;
153 rockchip,pvtm-number = <10>;
154 rockchip,pvtm-error = <1000>;
155 rockchip,pvtm-ref-temp = <35>;
156 rockchip,pvtm-temp-prop = <(-18) (-18)>;
157 rockchip,thermal-zone = "cpu-thermal";
159 opp-126000000 {
160 opp-hz = /bits/ 64 <126000000>;
161 opp-microvolt = <950000 950000 1350000>;
162 opp-microvolt-L0 = <950000 950000 1350000>;
163 opp-microvolt-L1 = <950000 950000 1350000>;
164 opp-microvolt-L2 = <950000 950000 1350000>;
165 opp-microvolt-L3 = <950000 950000 1350000>;
166 clock-latency-ns = <40000>;
168 opp-216000000 {
169 opp-hz = /bits/ 64 <216000000>;
170 opp-microvolt = <950000 950000 1350000>;
171 opp-microvolt-L0 = <950000 950000 1350000>;
172 opp-microvolt-L1 = <950000 950000 1350000>;
173 opp-microvolt-L2 = <950000 950000 1350000>;
174 opp-microvolt-L3 = <950000 950000 1350000>;
175 clock-latency-ns = <40000>;
177 opp-408000000 {
178 opp-hz = /bits/ 64 <408000000>;
179 opp-microvolt = <975000 975000 1350000>;
180 opp-microvolt-L0 = <975000 975000 1350000>;
181 opp-microvolt-L1 = <950000 950000 1350000>;
182 opp-microvolt-L2 = <950000 950000 1350000>;
183 opp-microvolt-L3 = <950000 950000 1350000>;
184 clock-latency-ns = <40000>;
186 opp-600000000 {
187 opp-hz = /bits/ 64 <600000000>;
188 opp-microvolt = <975000 975000 1350000>;
189 opp-microvolt-L0 = <975000 975000 1350000>;
190 opp-microvolt-L1 = <950000 950000 1350000>;
191 opp-microvolt-L2 = <950000 950000 1350000>;
192 opp-microvolt-L3 = <950000 950000 1350000>;
193 clock-latency-ns = <40000>;
195 opp-696000000 {
196 opp-hz = /bits/ 64 <696000000>;
197 opp-microvolt = <975000 975000 1350000>;
198 opp-microvolt-L0 = <975000 975000 1350000>;
199 opp-microvolt-L1 = <950000 950000 1350000>;
200 opp-microvolt-L2 = <950000 950000 1350000>;
201 opp-microvolt-L3 = <950000 950000 1350000>;
202 clock-latency-ns = <40000>;
204 opp-816000000 {
205 opp-hz = /bits/ 64 <816000000>;
206 opp-microvolt = <1075000 1075000 1350000>;
207 opp-microvolt-L0 = <1075000 1075000 1350000>;
208 opp-microvolt-L1 = <1050000 1050000 1350000>;
209 opp-microvolt-L2 = <1000000 1000000 1350000>;
210 opp-microvolt-L3 = <950000 950000 1350000>;
211 clock-latency-ns = <40000>;
212 opp-suspend;
214 opp-1008000000 {
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <1150000 1150000 1350000>;
217 opp-microvolt-L0 = <1150000 1150000 1350000>;
218 opp-microvolt-L1 = <1100000 1100000 1350000>;
219 opp-microvolt-L2 = <1050000 1050000 1350000>;
220 opp-microvolt-L3 = <1000000 1000000 1350000>;
221 clock-latency-ns = <40000>;
223 opp-1200000000 {
224 opp-hz = /bits/ 64 <1200000000>;
225 opp-microvolt = <1200000 1200000 1350000>;
226 opp-microvolt-L0 = <1200000 1200000 1350000>;
227 opp-microvolt-L1 = <1150000 1150000 1350000>;
228 opp-microvolt-L2 = <1100000 1100000 1350000>;
229 opp-microvolt-L3 = <1050000 1050000 1350000>;
230 clock-latency-ns = <40000>;
232 opp-1416000000 {
233 opp-hz = /bits/ 64 <1416000000>;
234 opp-microvolt = <1300000 1300000 1350000>;
235 opp-microvolt-L0 = <1300000 1300000 1350000>;
236 opp-microvolt-L1 = <1250000 1250000 1350000>;
237 opp-microvolt-L2 = <1200000 1200000 1350000>;
238 opp-microvolt-L3 = <1150000 1150000 1350000>;
239 clock-latency-ns = <40000>;
241 opp-1512000000 {
242 opp-hz = /bits/ 64 <1512000000>;
243 opp-microvolt = <1350000 1350000 1350000>;
244 opp-microvolt-L0 = <1350000 1350000 1350000>;
245 opp-microvolt-L1 = <1300000 1300000 1350000>;
246 opp-microvolt-L2 = <1250000 1250000 1350000>;
247 opp-microvolt-L3 = <1200000 1200000 1350000>;
248 clock-latency-ns = <40000>;
250 opp-1608000000 {
251 opp-hz = /bits/ 64 <1608000000>;
252 opp-microvolt = <1350000 1350000 1350000>;
253 opp-microvolt-L0 = <1350000 1350000 1350000>;
254 opp-microvolt-L1 = <1350000 1350000 1350000>;
255 opp-microvolt-L2 = <1300000 1300000 1350000>;
256 opp-microvolt-L3 = <1250000 1250000 1350000>;
257 clock-latency-ns = <40000>;
262 compatible = "simple-bus";
263 #address-cells = <2>;
264 #size-cells = <2>;
267 dmac_peri: dma-controller@ff250000 {
272 #dma-cells = <1>;
273 arm,pl330-broken-no-flushp;
274 arm,pl330-periph-burst;
276 clock-names = "apb_pclk";
279 dmac_bus_ns: dma-controller@ff600000 {
284 #dma-cells = <1>;
285 arm,pl330-broken-no-flushp;
286 arm,pl330-periph-burst;
288 clock-names = "apb_pclk";
292 dmac_bus_s: dma-controller@ffb20000 {
297 #dma-cells = <1>;
298 arm,pl330-broken-no-flushp;
299 arm,pl330-periph-burst;
301 clock-names = "apb_pclk";
307 compatible = "linaro,optee-tz";
312 reserved-memory {
313 #address-cells = <2>;
314 #size-cells = <2>;
327 dma-unusable@fe000000 {
333 compatible = "fixed-clock";
334 clock-frequency = <24000000>;
335 clock-output-names = "xin24m";
336 #clock-cells = <0>;
340 compatible = "arm,armv7-timer";
341 arm,cpu-registers-not-fw-configured;
346 clock-frequency = <24000000>;
347 arm,no-tick-in-suspend;
350 display-subsystem {
351 compatible = "rockchip,display-subsystem";
356 compatible = "rockchip,rk3288-dw-mshc";
357 max-frequency = <150000000>;
360 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
361 fifo-depth = <0x100>;
365 reset-names = "reset";
370 compatible = "rockchip,rk3288-dw-mshc";
371 max-frequency = <150000000>;
374 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
375 fifo-depth = <0x100>;
379 reset-names = "reset";
384 compatible = "rockchip,rk3288-dw-mshc";
385 max-frequency = <150000000>;
388 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
389 fifo-depth = <0x100>;
393 reset-names = "reset";
398 compatible = "rockchip,rk3288-dw-mshc";
399 max-frequency = <150000000>;
402 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
403 fifo-depth = <0x100>;
407 reset-names = "reset";
415 #io-channel-cells = <1>;
417 clock-names = "saradc", "apb_pclk";
419 reset-names = "saradc-apb";
424 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
426 clock-names = "spiclk", "apb_pclk";
428 dma-names = "tx", "rx";
430 pinctrl-names = "default";
431 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
433 #address-cells = <1>;
434 #size-cells = <0>;
439 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
441 clock-names = "spiclk", "apb_pclk";
443 dma-names = "tx", "rx";
445 pinctrl-names = "default";
446 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
448 #address-cells = <1>;
449 #size-cells = <0>;
454 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
456 clock-names = "spiclk", "apb_pclk";
458 dma-names = "tx", "rx";
460 pinctrl-names = "default";
461 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
463 #address-cells = <1>;
464 #size-cells = <0>;
469 compatible = "rockchip,rk3288-i2c";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 clock-names = "i2c";
476 pinctrl-names = "default";
477 pinctrl-0 = <&i2c0_xfer>;
482 compatible = "rockchip,rk3288-i2c";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 clock-names = "i2c";
489 pinctrl-names = "default";
490 pinctrl-0 = <&i2c1_xfer>;
495 compatible = "rockchip,rk3288-i2c";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 clock-names = "i2c";
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2c3_xfer>;
508 compatible = "rockchip,rk3288-i2c";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 clock-names = "i2c";
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c4_xfer>;
521 compatible = "rockchip,rk3288-i2c";
524 #address-cells = <1>;
525 #size-cells = <0>;
526 clock-names = "i2c";
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c5_xfer>;
534 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
537 reg-shift = <2>;
538 reg-io-width = <4>;
540 clock-names = "baudclk", "apb_pclk";
542 dma-names = "tx", "rx";
543 pinctrl-names = "default";
544 pinctrl-0 = <&uart0_xfer>;
549 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
552 reg-shift = <2>;
553 reg-io-width = <4>;
555 clock-names = "baudclk", "apb_pclk";
557 dma-names = "tx", "rx";
558 pinctrl-names = "default";
559 pinctrl-0 = <&uart1_xfer>;
564 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
567 reg-shift = <2>;
568 reg-io-width = <4>;
570 clock-names = "baudclk", "apb_pclk";
571 pinctrl-names = "default";
572 pinctrl-0 = <&uart2_xfer>;
577 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
580 reg-shift = <2>;
581 reg-io-width = <4>;
583 clock-names = "baudclk", "apb_pclk";
585 dma-names = "tx", "rx";
586 pinctrl-names = "default";
587 pinctrl-0 = <&uart3_xfer>;
592 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
595 reg-shift = <2>;
596 reg-io-width = <4>;
598 clock-names = "baudclk", "apb_pclk";
600 dma-names = "tx", "rx";
601 pinctrl-names = "default";
602 pinctrl-0 = <&uart4_xfer>;
606 thermal-zones {
608 polling-delay-passive = <1000>; /* milliseconds */
609 polling-delay = <5000>; /* milliseconds */
611 thermal-sensors = <&tsadc 0>;
614 cpu_thermal: cpu-thermal {
615 polling-delay-passive = <100>; /* milliseconds */
616 polling-delay = <5000>; /* milliseconds */
618 thermal-sensors = <&tsadc 1>;
638 cooling-maps {
641 cooling-device =
649 cooling-device =
658 gpu_thermal: gpu-thermal {
659 polling-delay-passive = <100>; /* milliseconds */
660 polling-delay = <5000>; /* milliseconds */
662 thermal-sensors = <&tsadc 2>;
677 cooling-maps {
680 cooling-device =
688 compatible = "rockchip,rk3288-tsadc";
692 clock-names = "tsadc", "apb_pclk";
693 assigned-clocks = <&cru SCLK_TSADC>;
694 assigned-clock-rates = <5000>;
696 reset-names = "tsadc-apb";
697 pinctrl-names = "gpio", "otpout";
698 pinctrl-0 = <&otp_pin>;
699 pinctrl-1 = <&otp_out>;
700 #thermal-sensor-cells = <1>;
702 rockchip,hw-tshut-temp = <95000>;
707 compatible = "rockchip,rk3288-gmac";
711 interrupt-names = "macirq", "eth_wake_irq";
717 clock-names = "stmmaceth",
722 reset-names = "stmmaceth";
727 compatible = "generic-ehci";
731 clock-names = "usbhost", "utmi";
733 phy-names = "usb";
739 compatible = "generic-ohci";
743 clock-names = "usbhost", "utmi";
745 phy-names = "usb";
750 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
755 clock-names = "otg";
758 phy-names = "usb2-phy";
759 snps,reset-phy-on-wake;
764 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
769 clock-names = "otg";
771 g-np-tx-fifo-size = <16>;
772 g-rx-fifo-size = <280>;
773 g-tx-fifo-size = <256 128 128 64 32 16>;
775 phy-names = "usb2-phy";
780 compatible = "generic-ehci";
788 compatible = "rockchip,rk3288-i2c";
791 #address-cells = <1>;
792 #size-cells = <0>;
793 clock-names = "i2c";
795 pinctrl-names = "default";
796 pinctrl-0 = <&i2c2_xfer>;
801 compatible = "rockchip,rk3288-pwm";
803 #pwm-cells = <3>;
804 pinctrl-names = "active";
805 pinctrl-0 = <&pwm0_pin>;
807 clock-names = "pwm";
812 compatible = "rockchip,rk3288-pwm";
814 #pwm-cells = <3>;
815 pinctrl-names = "active";
816 pinctrl-0 = <&pwm1_pin>;
818 clock-names = "pwm";
823 compatible = "rockchip,rk3288-pwm";
825 #pwm-cells = <3>;
826 pinctrl-names = "active";
827 pinctrl-0 = <&pwm2_pin>;
829 clock-names = "pwm";
834 compatible = "rockchip,rk3288-pwm";
836 #pwm-cells = <3>;
837 pinctrl-names = "active";
838 pinctrl-0 = <&pwm3_pin>;
840 clock-names = "pwm";
845 compatible = "rockchip,rk3288-timer";
849 clock-names = "pclk", "timer";
853 compatible = "mmio-sram";
855 #address-cells = <1>;
856 #size-cells = <1>;
858 smp-sram@0 {
859 compatible = "rockchip,rk3066-smp-sram";
865 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
869 pmu: power-management@ff730000 {
870 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
873 power: power-controller {
874 compatible = "rockchip,rk3288-power-controller";
875 #power-domain-cells = <1>;
876 #address-cells = <1>;
877 #size-cells = <0>;
879 assigned-clocks = <&cru SCLK_EDP_24M>;
880 assigned-clock-parents = <&xin24m>;
905 power-domain@RK3288_PD_VIO {
948 power-domain@RK3288_PD_HEVC {
962 power-domain@RK3288_PD_VIDEO {
973 power-domain@RK3288_PD_GPU {
981 reboot-mode {
982 compatible = "syscon-reboot-mode";
984 mode-normal = <BOOT_NORMAL>;
985 mode-recovery = <BOOT_RECOVERY>;
986 mode-bootloader = <BOOT_FASTBOOT>;
987 mode-loader = <BOOT_BL_DOWNLOAD>;
988 mode-ums = <BOOT_UMS>;
993 compatible = "rockchip,rk3288-sgrf", "syscon";
997 cru: clock-controller@ff760000 {
998 compatible = "rockchip,rk3288-cru";
1001 #clock-cells = <1>;
1002 #reset-cells = <1>;
1003 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
1008 assigned-clock-rates = <594000000>, <500000000>,
1016 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
1019 edp_phy: edp-phy {
1020 compatible = "rockchip,rk3288-dp-phy";
1022 clock-names = "24m";
1023 #phy-cells = <0>;
1027 io_domains: io-domains {
1028 compatible = "rockchip,rk3288-io-voltage-domain";
1032 mipi_phy_rx0: mipi-phy-rx0 {
1033 compatible = "rockchip,rk3288-mipi-dphy";
1035 clock-names = "dphy-ref", "pclk";
1040 compatible = "rockchip,rk3288-lvds";
1042 phy-names = "phy";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1056 remote-endpoint = <&vopb_out_lvds>;
1061 remote-endpoint = <&vopl_out_lvds>;
1068 compatible = "rockchip,rk3288-rgb";
1069 pinctrl-names = "default", "sleep";
1070 pinctrl-0 = <&lcdc_rgb_pins>;
1071 pinctrl-1 = <&lcdc_sleep_pins>;
1073 phy-names = "phy";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1087 remote-endpoint = <&vopb_out_rgb>;
1092 remote-endpoint = <&vopl_out_rgb>;
1099 compatible = "rockchip,rk3288-usb-phy";
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1104 usbphy0: usb-phy@320 {
1105 #phy-cells = <0>;
1108 clock-names = "phyclk";
1109 #clock-cells = <0>;
1111 reset-names = "phy-reset";
1113 interrupt-names = "otg-bvalid";
1116 usbphy1: usb-phy@334 {
1117 #phy-cells = <0>;
1120 clock-names = "phyclk";
1121 #clock-cells = <0>;
1123 reset-names = "phy-reset";
1126 usbphy2: usb-phy@348 {
1127 #phy-cells = <0>;
1130 clock-names = "phyclk";
1131 #clock-cells = <0>;
1133 reset-names = "phy-reset";
1138 compatible = "rockchip,rk3288-pvtm";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1146 clock-names = "clk";
1148 reset-names = "rst";
1153 clock-names = "clk";
1155 reset-names = "rst";
1161 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1169 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1171 #sound-dai-cells = <0>;
1173 clock-names = "mclk", "hclk";
1175 dma-names = "tx";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&spdif_tx>;
1184 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1186 #sound-dai-cells = <0>;
1189 clock-names = "i2s_clk", "i2s_hclk";
1190 assigned-clocks = <&cru SCLK_I2S_SRC>;
1191 assigned-clock-parents = <&cru PLL_GPLL>;
1193 dma-names = "tx", "rx";
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&i2s0_bus>;
1197 reset-names = "reset-m";
1198 rockchip,playback-channels = <8>;
1199 rockchip,capture-channels = <2>;
1204 compatible = "rockchip,cryptov1-rng";
1207 clock-names = "clk_crypto", "hclk_crypto";
1208 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
1209 assigned-clock-rates = <150000000>, <100000000>;
1214 compatible = "rockchip,rk3288-crypto";
1219 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
1221 reset-names = "crypto-rst";
1226 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1228 #sound-dai-cells = <0>;
1230 clock-names = "mclk", "hclk";
1232 dma-names = "tx";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&spdif_tx>;
1247 clock-names = "aclk_iep", "hclk_iep";
1248 power-domains = <&power RK3288_PD_VIO>;
1258 interrupt-names = "iep_mmu";
1260 clock-names = "aclk", "iface";
1261 #iommu-cells = <0>;
1266 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1269 power-domains = <&power RK3288_PD_VIO>;
1275 clock-names =
1279 pinctrl-names =
1284 pinctrl-0 = <&isp_mipi>;
1285 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1286 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1287 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1289 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1290 pinctrl-5 = <&isp_mipi>;
1291 pinctrl-6 = <&isp_mipi &isp_prelight>;
1292 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1293 pinctrl-8 = <&isp_flash_trigger>;
1306 compatible = "rockchip,rk3288-rkisp1";
1309 interrupt-names = "isp_irq";
1313 clock-names = "clk_isp", "aclk_isp",
1316 assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>;
1317 assigned-clock-rates = <400000000>, <400000000>;
1318 power-domains = <&power RK3288_PD_VIO>;
1327 interrupt-names = "isp_mmu";
1329 clock-names = "aclk", "iface";
1330 #iommu-cells = <0>;
1331 rockchip,disable-mmu-reset;
1336 compatible = "rockchip,rk3288-rga";
1340 clock-names = "aclk", "hclk", "sclk";
1341 power-domains = <&power RK3288_PD_VIO>;
1343 reset-names = "core", "axi", "ahb";
1348 compatible = "rockchip,rk3288-vop-big";
1350 reg-names = "regs", "gamma_lut";
1353 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1354 power-domains = <&power RK3288_PD_VIO>;
1356 reset-names = "axi", "ahb", "dclk";
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1366 remote-endpoint = <&hdmi_in_vopb>;
1371 remote-endpoint = <&edp_in_vopb>;
1376 remote-endpoint = <&dsi0_in_vopb>;
1381 remote-endpoint = <&dsi1_in_vopb>;
1386 remote-endpoint = <&lvds_in_vopb>;
1391 remote-endpoint = <&rgb_in_vopb>;
1400 interrupt-names = "vopb_mmu";
1402 clock-names = "aclk", "iface";
1403 power-domains = <&power RK3288_PD_VIO>;
1404 #iommu-cells = <0>;
1405 rockchip,disable-device-link-resume;
1410 compatible = "rockchip,rk3288-vop-lit";
1412 reg-names = "regs", "gamma_lut";
1415 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1416 power-domains = <&power RK3288_PD_VIO>;
1418 reset-names = "axi", "ahb", "dclk";
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1428 remote-endpoint = <&hdmi_in_vopl>;
1433 remote-endpoint = <&edp_in_vopl>;
1438 remote-endpoint = <&dsi0_in_vopl>;
1443 remote-endpoint = <&dsi1_in_vopl>;
1448 remote-endpoint = <&lvds_in_vopl>;
1453 remote-endpoint = <&rgb_in_vopl>;
1462 interrupt-names = "vopl_mmu";
1464 clock-names = "aclk", "iface";
1465 power-domains = <&power RK3288_PD_VIO>;
1466 #iommu-cells = <0>;
1467 rockchip,disable-device-link-resume;
1472 compatible = "rockchip,cif", "rockchip,rk3288-cif";
1477 clock-names = "aclk_cif0", "hclk_cif0",
1480 reset-names = "rst_cif";
1481 pinctrl-names = "cif_pin_all";
1482 pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
1485 power-domains = <&power RK3288_PD_VIO>;
1490 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1494 clock-names = "ref", "pclk";
1496 reset-names = "apb";
1497 power-domains = <&power RK3288_PD_VIO>;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1509 remote-endpoint = <&vopb_out_dsi0>;
1513 remote-endpoint = <&vopl_out_dsi0>;
1520 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1524 clock-names = "ref", "pclk";
1526 reset-names = "apb";
1527 power-domains = <&power RK3288_PD_VIO>;
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1543 remote-endpoint = <&vopb_out_dsi1>;
1547 remote-endpoint = <&vopl_out_dsi1>;
1553 video_phy: video-phy@ff96c000 {
1554 compatible = "rockchip,rk3288-video-phy";
1557 clock-names = "pclk";
1559 reset-names = "rst";
1560 power-domains = <&power RK3288_PD_VIO>;
1561 #phy-cells = <0>;
1566 compatible = "rockchip,rk3288-dp";
1571 clock-names = "dp", "pclk", "spdif";
1572 assigned-clocks = <&cru SCLK_EDP_24M>;
1573 assigned-clock-parents = <&xin24m>;
1574 power-domains = <&power RK3288_PD_VIO>;
1576 reset-names = "dp";
1581 #address-cells = <1>;
1582 #size-cells = <0>;
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1589 remote-endpoint = <&vopb_out_edp>;
1593 remote-endpoint = <&vopl_out_edp>;
1600 compatible = "rockchip,rk3288-dw-hdmi";
1602 reg-io-width = <4>;
1603 #sound-dai-cells = <0>;
1607 clock-names = "iahb", "isfr", "cec";
1608 pinctrl-names = "default", "sleep";
1609 pinctrl-0 = <&hdmi_ddc>;
1610 pinctrl-1 = <&hdmi_gpio>;
1611 power-domains = <&power RK3288_PD_VIO>;
1612 unsupported-yuv-input;
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1621 remote-endpoint = <&vopb_out_hdmi>;
1625 remote-endpoint = <&vopl_out_hdmi>;
1631 vpu: video-codec@ff9a0000 {
1632 compatible = "rockchip,rk3288-vpu";
1636 interrupt-names = "vepu", "vdpu";
1638 clock-names = "aclk", "hclk";
1640 power-domains = <&power RK3288_PD_VIDEO>;
1644 mpp_srv: mpp-srv {
1645 compatible = "rockchip,mpp-service";
1646 rockchip,taskqueue-count = <2>;
1647 rockchip,resetgroup-count = <2>;
1652 compatible = "rockchip,vpu-encoder-v1";
1655 interrupt-names = "irq_enc";
1657 clock-names = "aclk_vcodec", "hclk_vcodec";
1659 reset-names = "shared_video_a", "shared_video_h";
1660 assigned-clocks = <&cru ACLK_VCODEC>;
1661 assigned-clock-rates = <400000000>;
1663 power-domains = <&power RK3288_PD_VIDEO>;
1665 rockchip,taskqueue-node = <0>;
1666 rockchip,resetgroup-node = <0>;
1671 compatible = "rockchip,vpu-decoder-rk3288", "rockchip,vpu-decoder-v1";
1674 interrupt-names = "irq_dec";
1676 clock-names = "aclk_vcodec", "hclk_vcodec";
1677 rockchip,normal-rates = <300000000>, <0>;
1678 rockchip,advanced-rates = <600000000>, <0>;
1680 reset-names = "shared_video_a", "shared_video_h";
1681 assigned-clocks = <&cru ACLK_VCODEC>;
1682 assigned-clock-rates = <400000000>;
1684 power-domains = <&power RK3288_PD_VIDEO>;
1686 rockchip,taskqueue-node = <0>;
1687 rockchip,resetgroup-node = <0>;
1695 interrupt-names = "vpu_mmu";
1697 clock-names = "aclk", "iface";
1698 #iommu-cells = <0>;
1699 power-domains = <&power RK3288_PD_VIDEO>;
1704 compatible = "rockchip,hevc-decoder";
1707 interrupt-names = "irq_dec";
1710 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1712 rockchip,normal-rates = <300000000>, <0>, <200000000>,
1714 rockchip,advanced-rates = <500000000>, <0>, <400000000>,
1716 rockchip,default-max-load = <2088960>;
1718 reset-names = "video_core";
1724 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1727 assigned-clock-rates = <400000000>, <100000000>,
1731 rockchip,taskqueue-node = <1>;
1732 rockchip,resetgroup-node = <1>;
1733 power-domains = <&power RK3288_PD_HEVC>;
1741 interrupt-names = "hevc_mmu";
1743 clock-names = "aclk", "iface";
1744 power-domains = <&power RK3288_PD_HEVC>;
1745 #iommu-cells = <0>;
1750 compatible = "rockchip,rk3288-mali", "arm,mali-t760",
1752 "arm,mali-midgard";
1757 interrupt-names = "job", "mmu", "gpu";
1759 clock-names = "clk_mali";
1760 operating-points-v2 = <&gpu_opp_table>;
1761 #cooling-cells = <2>; /* min followed by max */
1762 power-domains = <&power RK3288_PD_GPU>;
1769 compatible = "arm,mali-simple-power-model";
1770 static-coefficient = <411000>;
1771 dynamic-coefficient = <733>;
1772 ts = <32000 4700 (-80) 2>;
1773 thermal-zone = "gpu-thermal";
1777 gpu_opp_table: gpu-opp-table {
1778 compatible = "operating-points-v2";
1781 nvmem-cells = <&performance>, <&performance_w>;
1782 nvmem-cell-names = "performance", "performance-w";
1783 rockchip,bin-scaling-sel = <
1790 opp-100000000 {
1791 opp-hz = /bits/ 64 <100000000>;
1792 opp-microvolt = <950000>;
1794 opp-200000000 {
1795 opp-hz = /bits/ 64 <200000000>;
1796 opp-microvolt = <950000>;
1798 opp-300000000 {
1799 opp-hz = /bits/ 64 <300000000>;
1800 opp-microvolt = <1000000>;
1802 opp-420000000 {
1803 opp-hz = /bits/ 64 <420000000>;
1804 opp-microvolt = <1100000>;
1806 opp-600000000 {
1807 opp-hz = /bits/ 64 <600000000>;
1808 opp-microvolt = <1250000>;
1883 compatible = "rockchip,rk3288-efuse";
1885 #address-cells = <1>;
1886 #size-cells = <1>;
1888 clock-names = "pclk_efuse";
1890 special_function: special-function@5 {
1894 package_info: package-info@5 {
1898 process_version: process-version@6 {
1902 cpu_id: cpu-id@7 {
1918 gic: interrupt-controller@ffc01000 {
1919 compatible = "arm,gic-400";
1920 interrupt-controller;
1921 #interrupt-cells = <3>;
1922 #address-cells = <0>;
1931 rockchip_system_monitor: rockchip-system-monitor {
1932 compatible = "rockchip,system-monitor";
1935 rockchip_suspend: rockchip-suspend {
1936 compatible = "rockchip,pm-rk3288";
1938 rockchip,sleep-mode-config = <
1947 rockchip,wakeup-config = <
1952 rockchip,pwm-regulator-config = <
1960 compatible = "rockchip,rk3288-pinctrl";
1963 #address-cells = <2>;
1964 #size-cells = <2>;
1968 compatible = "rockchip,gpio-bank";
1973 gpio-controller;
1974 #gpio-cells = <2>;
1976 interrupt-controller;
1977 #interrupt-cells = <2>;
1981 compatible = "rockchip,gpio-bank";
1986 gpio-controller;
1987 #gpio-cells = <2>;
1989 interrupt-controller;
1990 #interrupt-cells = <2>;
1994 compatible = "rockchip,gpio-bank";
1999 gpio-controller;
2000 #gpio-cells = <2>;
2002 interrupt-controller;
2003 #interrupt-cells = <2>;
2007 compatible = "rockchip,gpio-bank";
2012 gpio-controller;
2013 #gpio-cells = <2>;
2015 interrupt-controller;
2016 #interrupt-cells = <2>;
2020 compatible = "rockchip,gpio-bank";
2025 gpio-controller;
2026 #gpio-cells = <2>;
2028 interrupt-controller;
2029 #interrupt-cells = <2>;
2033 compatible = "rockchip,gpio-bank";
2038 gpio-controller;
2039 #gpio-cells = <2>;
2041 interrupt-controller;
2042 #interrupt-cells = <2>;
2046 compatible = "rockchip,gpio-bank";
2051 gpio-controller;
2052 #gpio-cells = <2>;
2054 interrupt-controller;
2055 #interrupt-cells = <2>;
2059 compatible = "rockchip,gpio-bank";
2064 gpio-controller;
2065 #gpio-cells = <2>;
2067 interrupt-controller;
2068 #interrupt-cells = <2>;
2072 compatible = "rockchip,gpio-bank";
2077 gpio-controller;
2078 #gpio-cells = <2>;
2080 interrupt-controller;
2081 #interrupt-cells = <2>;
2084 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2085 bias-disable;
2086 drive-strength = <12>;
2091 #include "rk3288-pinctrl.dtsi"