Lines Matching full:cru
7 #include <dt-bindings/clock/rk3288-cru.h>
79 resets = <&cru SRST_CORE0>;
83 clocks = <&cru ARMCLK>;
91 resets = <&cru SRST_CORE1>;
95 clocks = <&cru ARMCLK>;
103 resets = <&cru SRST_CORE2>;
107 clocks = <&cru ARMCLK>;
115 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ARMCLK>;
128 clocks = <&cru PLL_APLL>;
275 clocks = <&cru ACLK_DMAC2>;
287 clocks = <&cru ACLK_DMAC1>;
300 clocks = <&cru ACLK_DMAC1>;
358 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
359 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
364 resets = <&cru SRST_MMC0>;
372 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
373 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
378 resets = <&cru SRST_SDIO0>;
386 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
387 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
392 resets = <&cru SRST_SDIO1>;
400 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
401 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
406 resets = <&cru SRST_EMMC>;
416 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
418 resets = <&cru SRST_SARADC>;
425 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
440 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
455 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
475 clocks = <&cru PCLK_I2C0>;
488 clocks = <&cru PCLK_I2C1>;
501 clocks = <&cru PCLK_I2C3>;
514 clocks = <&cru PCLK_I2C4>;
527 clocks = <&cru PCLK_I2C5>;
539 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
554 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
569 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
582 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
597 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
691 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
693 assigned-clocks = <&cru SCLK_TSADC>;
695 resets = <&cru SRST_TSADC>;
713 clocks = <&cru SCLK_MAC>,
714 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
715 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
716 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
721 resets = <&cru SRST_MAC>;
730 clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
742 clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
754 clocks = <&cru HCLK_USBHOST1>;
768 clocks = <&cru HCLK_OTG0>;
783 clocks = <&cru HCLK_HSIC>;
794 clocks = <&cru PCLK_I2C2>;
806 clocks = <&cru PCLK_RKPWM>;
817 clocks = <&cru PCLK_RKPWM>;
828 clocks = <&cru PCLK_RKPWM>;
839 clocks = <&cru PCLK_RKPWM>;
848 clocks = <&cru PCLK_TIMER>, <&xin24m>;
879 assigned-clocks = <&cru SCLK_EDP_24M>;
907 clocks = <&cru ACLK_IEP>,
908 <&cru ACLK_ISP>,
909 <&cru ACLK_RGA>,
910 <&cru ACLK_VIP>,
911 <&cru ACLK_VOP0>,
912 <&cru ACLK_VOP1>,
913 <&cru DCLK_VOP0>,
914 <&cru DCLK_VOP1>,
915 <&cru HCLK_IEP>,
916 <&cru HCLK_ISP>,
917 <&cru HCLK_RGA>,
918 <&cru HCLK_VIP>,
919 <&cru HCLK_VOP0>,
920 <&cru HCLK_VOP1>,
921 <&cru PCLK_EDP_CTRL>,
922 <&cru PCLK_HDMI_CTRL>,
923 <&cru PCLK_LVDS_PHY>,
924 <&cru PCLK_MIPI_CSI>,
925 <&cru PCLK_MIPI_DSI0>,
926 <&cru PCLK_MIPI_DSI1>,
927 <&cru SCLK_EDP_24M>,
928 <&cru SCLK_EDP>,
929 <&cru SCLK_HDMI_CEC>,
930 <&cru SCLK_ISP_JPE>,
931 <&cru SCLK_ISP>,
932 <&cru SCLK_RGA>;
950 clocks = <&cru ACLK_HEVC>,
951 <&cru SCLK_HEVC_CABAC>,
952 <&cru SCLK_HEVC_CORE>;
964 clocks = <&cru ACLK_VCODEC>,
965 <&cru HCLK_VCODEC>;
975 clocks = <&cru ACLK_GPU>;
997 cru: clock-controller@ff760000 { label
998 compatible = "rockchip,rk3288-cru";
1003 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
1004 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
1005 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
1006 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
1007 <&cru ACLK_VIO0>, <&cru ACLK_VIO1>;
1021 clocks = <&cru SCLK_EDP_24M>;
1034 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
1107 clocks = <&cru SCLK_OTGPHY0>;
1110 resets = <&cru SRST_USBOTG_PHY>;
1119 clocks = <&cru SCLK_OTGPHY1>;
1122 resets = <&cru SRST_USBHOST0_PHY>;
1129 clocks = <&cru SCLK_OTGPHY2>;
1132 resets = <&cru SRST_USBHOST1_PHY>;
1145 clocks = <&cru SCLK_PVTM_CORE>;
1147 resets = <&cru SRST_CORE_PVTM>;
1152 clocks = <&cru SCLK_PVTM_GPU>;
1154 resets = <&cru SRST_GPU_PVTM>;
1163 clocks = <&cru PCLK_WDT>;
1172 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
1188 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
1190 assigned-clocks = <&cru SCLK_I2S_SRC>;
1191 assigned-clock-parents = <&cru PLL_GPLL>;
1196 resets = <&cru SRST_I2S0>;
1206 clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
1208 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
1217 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
1218 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
1220 resets = <&cru SRST_CRYPTO>;
1229 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
1246 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1259 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1271 <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1272 <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1273 <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1274 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1298 rockchip,cru = <&cru>;
1310 clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>,
1311 <&cru HCLK_ISP>, <&cru PCLK_ISP_IN>,
1312 <&cru SCLK_ISP_JPE>;
1316 assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>;
1328 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1339 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1342 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1352 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1355 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1401 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1414 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1417 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1463 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1475 clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>,
1476 <&cru PCLK_VIP_IN>, <&cru SCLK_VIP_OUT>;
1479 resets = <&cru SRST_VIP>;
1484 rockchip,cru = <&cru>;
1493 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1495 resets = <&cru SRST_MIPIDSI0>;
1523 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
1525 resets = <&cru SRST_MIPIDSI1>;
1556 clocks = <&cru PCLK_LVDS_PHY>;
1558 resets = <&cru SRST_LVDS_PHY>;
1569 clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>,
1570 <&cru SCLK_EDP>;
1572 assigned-clocks = <&cru SCLK_EDP_24M>;
1575 resets = <&cru SRST_EDP>;
1606 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1637 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1656 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1658 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1660 assigned-clocks = <&cru ACLK_VCODEC>;
1675 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1679 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1681 assigned-clocks = <&cru ACLK_VCODEC>;
1696 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1708 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CORE>,
1709 <&cru SCLK_HEVC_CABAC>;
1717 resets = <&cru SRST_HEVC>;
1724 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1725 <&cru SCLK_HEVC_CORE>,
1726 <&cru SCLK_HEVC_CABAC>;
1742 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1758 clocks = <&cru ACLK_GPU>;
1780 clocks = <&cru PLL_GPLL>;
1887 clocks = <&cru PCLK_EFUSE256>;
1971 clocks = <&cru PCLK_GPIO0>;
1984 clocks = <&cru PCLK_GPIO1>;
1997 clocks = <&cru PCLK_GPIO2>;
2010 clocks = <&cru PCLK_GPIO3>;
2023 clocks = <&cru PCLK_GPIO4>;
2036 clocks = <&cru PCLK_GPIO5>;
2049 clocks = <&cru PCLK_GPIO6>;
2062 clocks = <&cru PCLK_GPIO7>;
2075 clocks = <&cru PCLK_GPIO8>;