Lines Matching +full:sclk +full:- +full:strength
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
37 operating-points-v2 = <&cpu0_opp_table>;
38 #cooling-cells = <2>; /* min followed by max */
39 clock-latency = <40000>;
41 enable-method = "psci";
46 compatible = "arm,cortex-a7";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
51 enable-method = "psci";
56 compatible = "arm,cortex-a7";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
61 enable-method = "psci";
66 compatible = "arm,cortex-a7";
69 operating-points-v2 = <&cpu0_opp_table>;
70 #cooling-cells = <2>; /* min followed by max */
71 enable-method = "psci";
76 compatible = "operating-points-v2";
77 opp-shared;
79 opp-408000000 {
80 opp-hz = /bits/ 64 <408000000>;
81 opp-microvolt = <950000>;
82 clock-latency-ns = <40000>;
83 opp-suspend;
85 opp-600000000 {
86 opp-hz = /bits/ 64 <600000000>;
87 opp-microvolt = <975000>;
89 opp-816000000 {
90 opp-hz = /bits/ 64 <816000000>;
91 opp-microvolt = <1000000>;
93 opp-1008000000 {
94 opp-hz = /bits/ 64 <1008000000>;
95 opp-microvolt = <1175000>;
97 opp-1200000000 {
98 opp-hz = /bits/ 64 <1200000000>;
99 opp-microvolt = <1275000>;
104 compatible = "simple-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
114 #dma-cells = <1>;
115 arm,pl330-periph-burst;
117 clock-names = "apb_pclk";
121 arm-pmu {
122 compatible = "arm,cortex-a7-pmu";
127 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
131 compatible = "arm,psci-1.0", "arm,psci-0.2";
136 compatible = "arm,armv7-timer";
137 arm,cpu-registers-not-fw-configured;
142 clock-frequency = <24000000>;
146 compatible = "fixed-clock";
147 clock-frequency = <24000000>;
148 clock-output-names = "xin24m";
149 #clock-cells = <0>;
152 display_subsystem: display-subsystem {
153 compatible = "rockchip,display-subsystem";
158 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
161 clock-names = "i2s_clk", "i2s_hclk";
164 dma-names = "tx", "rx";
166 reset-names = "reset-m";
167 pinctrl-names = "default";
168 pinctrl-0 = <&i2s1_bus>;
173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
176 clock-names = "i2s_clk", "i2s_hclk";
179 dma-names = "tx", "rx";
181 reset-names = "reset-m";
186 compatible = "rockchip,rk3228-spdif";
190 clock-names = "mclk", "hclk";
192 dma-names = "tx";
193 pinctrl-names = "default";
194 pinctrl-0 = <&spdif_tx>;
199 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
202 clock-names = "i2s_clk", "i2s_hclk";
205 dma-names = "tx", "rx";
207 reset-names = "reset-m";
212 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
214 #address-cells = <1>;
215 #size-cells = <1>;
217 io_domains: io-domains {
218 compatible = "rockchip,rk3228-io-voltage-domain";
222 u2phy0: usb2-phy@760 {
223 compatible = "rockchip,rk3228-usb2phy";
226 clock-names = "phyclk";
227 clock-output-names = "usb480m_phy0";
228 #clock-cells = <0>;
231 u2phy0_otg: otg-port {
235 interrupt-names = "otg-bvalid", "otg-id",
237 #phy-cells = <0>;
241 u2phy0_host: host-port {
243 interrupt-names = "linestate";
244 #phy-cells = <0>;
249 u2phy1: usb2-phy@800 {
250 compatible = "rockchip,rk3228-usb2phy";
253 clock-names = "phyclk";
254 clock-output-names = "usb480m_phy1";
255 #clock-cells = <0>;
258 u2phy1_otg: otg-port {
260 interrupt-names = "linestate";
261 #phy-cells = <0>;
265 u2phy1_host: host-port {
267 interrupt-names = "linestate";
268 #phy-cells = <0>;
275 compatible = "snps,dw-apb-uart";
278 clock-frequency = <24000000>;
280 clock-names = "baudclk", "apb_pclk";
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
283 reg-shift = <2>;
284 reg-io-width = <4>;
289 compatible = "snps,dw-apb-uart";
292 clock-frequency = <24000000>;
294 clock-names = "baudclk", "apb_pclk";
295 pinctrl-names = "default";
296 pinctrl-0 = <&uart1_xfer>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
303 compatible = "snps,dw-apb-uart";
306 clock-frequency = <24000000>;
308 clock-names = "baudclk", "apb_pclk";
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart2_xfer>;
311 reg-shift = <2>;
312 reg-io-width = <4>;
317 compatible = "rockchip,rk3228-efuse";
320 clock-names = "pclk_efuse";
321 #address-cells = <1>;
322 #size-cells = <1>;
334 compatible = "rockchip,rk3228-i2c";
337 #address-cells = <1>;
338 #size-cells = <0>;
339 clock-names = "i2c";
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c0_xfer>;
347 compatible = "rockchip,rk3228-i2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 clock-names = "i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c1_xfer>;
360 compatible = "rockchip,rk3228-i2c";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 clock-names = "i2c";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c2_xfer>;
373 compatible = "rockchip,rk3228-i2c";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clock-names = "i2c";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c3_xfer>;
386 compatible = "rockchip,rk3228-spi";
389 #address-cells = <1>;
390 #size-cells = <0>;
392 clock-names = "spiclk", "apb_pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
399 compatible = "snps,dw-wdt";
407 compatible = "rockchip,rk3288-pwm";
409 #pwm-cells = <3>;
411 clock-names = "pwm";
412 pinctrl-names = "active";
413 pinctrl-0 = <&pwm0_pin>;
418 compatible = "rockchip,rk3288-pwm";
420 #pwm-cells = <3>;
422 clock-names = "pwm";
423 pinctrl-names = "active";
424 pinctrl-0 = <&pwm1_pin>;
429 compatible = "rockchip,rk3288-pwm";
431 #pwm-cells = <3>;
433 clock-names = "pwm";
434 pinctrl-names = "active";
435 pinctrl-0 = <&pwm2_pin>;
440 compatible = "rockchip,rk3288-pwm";
442 #pwm-cells = <2>;
444 clock-names = "pwm";
445 pinctrl-names = "active";
446 pinctrl-0 = <&pwm3_pin>;
451 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
455 clock-names = "timer", "pclk";
458 cru: clock-controller@110e0000 {
459 compatible = "rockchip,rk3228-cru";
462 #clock-cells = <1>;
463 #reset-cells = <1>;
464 assigned-clocks =
470 assigned-clock-rates =
478 thermal-zones {
479 cpu_thermal: cpu-thermal {
480 polling-delay-passive = <100>; /* milliseconds */
481 polling-delay = <5000>; /* milliseconds */
483 thermal-sensors = <&tsadc 0>;
503 cooling-maps {
506 cooling-device =
514 cooling-device =
525 compatible = "rockchip,rk3228-tsadc";
529 clock-names = "tsadc", "apb_pclk";
530 assigned-clocks = <&cru SCLK_TSADC>;
531 assigned-clock-rates = <32768>;
533 reset-names = "tsadc-apb";
534 pinctrl-names = "gpio", "otpout";
535 pinctrl-0 = <&otp_pin>;
536 pinctrl-1 = <&otp_out>;
537 #thermal-sensor-cells = <1>;
538 rockchip,hw-tshut-temp = <95000>;
542 hdmi_phy: hdmi-phy@12030000 {
543 compatible = "rockchip,rk3228-hdmi-phy";
546 clock-names = "sysclk", "refoclk", "refpclk";
547 #clock-cells = <0>;
548 clock-output-names = "hdmiphy_phy";
549 #phy-cells = <0>;
554 compatible = "rockchip,rk3228-mali", "arm,mali-400";
562 interrupt-names = "gp",
569 clock-names = "bus", "core";
579 clock-names = "aclk", "iface";
580 #iommu-cells = <0>;
589 clock-names = "aclk", "iface";
590 #iommu-cells = <0>;
595 compatible = "rockchip,rk3228-vop";
599 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
601 reset-names = "axi", "ahb", "dclk";
606 #address-cells = <1>;
607 #size-cells = <0>;
611 remote-endpoint = <&hdmi_in_vop>;
621 clock-names = "aclk", "iface";
622 #iommu-cells = <0>;
627 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
631 clock-names = "aclk", "hclk", "sclk";
633 reset-names = "core", "axi", "ahb";
641 clock-names = "aclk", "iface";
642 #iommu-cells = <0>;
647 compatible = "rockchip,rk3228-dw-hdmi";
649 reg-io-width = <4>;
651 assigned-clocks = <&cru SCLK_HDMI_PHY>;
652 assigned-clock-parents = <&hdmi_phy>;
654 clock-names = "iahb", "isfr", "cec";
655 pinctrl-names = "default";
656 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
658 reset-names = "hdmi";
660 phy-names = "hdmi";
666 #address-cells = <1>;
667 #size-cells = <0>;
670 remote-endpoint = <&vop_out_hdmi>;
677 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
682 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
683 fifo-depth = <0x100>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
690 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
695 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
696 fifo-depth = <0x100>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
703 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
706 clock-frequency = <37500000>;
707 max-frequency = <37500000>;
710 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
711 bus-width = <8>;
712 rockchip,default-sample-phase = <158>;
713 fifo-depth = <0x100>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
717 reset-names = "reset";
722 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
727 clock-names = "otg";
729 g-np-tx-fifo-size = <16>;
730 g-rx-fifo-size = <280>;
731 g-tx-fifo-size = <256 128 128 64 32 16>;
733 phy-names = "usb2-phy";
738 compatible = "generic-ehci";
743 phy-names = "usb";
748 compatible = "generic-ohci";
753 phy-names = "usb";
758 compatible = "generic-ehci";
763 phy-names = "usb";
768 compatible = "generic-ohci";
773 phy-names = "usb";
778 compatible = "generic-ehci";
783 phy-names = "usb";
788 compatible = "generic-ohci";
793 phy-names = "usb";
798 compatible = "rockchip,rk3228-gmac";
801 interrupt-names = "macirq";
806 clock-names = "stmmaceth", "mac_clk_rx",
811 reset-names = "stmmaceth";
816 gic: interrupt-controller@32010000 {
817 compatible = "arm,gic-400";
818 interrupt-controller;
819 #interrupt-cells = <3>;
820 #address-cells = <0>;
830 compatible = "rockchip,rk3228-pinctrl";
832 #address-cells = <1>;
833 #size-cells = <1>;
837 compatible = "rockchip,gpio-bank";
840 clock-names = "bus";
843 gpio-controller;
844 #gpio-cells = <2>;
846 interrupt-controller;
847 #interrupt-cells = <2>;
851 compatible = "rockchip,gpio-bank";
854 clock-names = "bus";
857 gpio-controller;
858 #gpio-cells = <2>;
860 interrupt-controller;
861 #interrupt-cells = <2>;
865 compatible = "rockchip,gpio-bank";
868 clock-names = "bus";
871 gpio-controller;
872 #gpio-cells = <2>;
874 interrupt-controller;
875 #interrupt-cells = <2>;
879 compatible = "rockchip,gpio-bank";
882 clock-names = "bus";
885 gpio-controller;
886 #gpio-cells = <2>;
888 interrupt-controller;
889 #interrupt-cells = <2>;
892 pcfg_pull_up: pcfg-pull-up {
893 bias-pull-up;
896 pcfg_pull_down: pcfg-pull-down {
897 bias-pull-down;
900 pcfg_pull_none: pcfg-pull-none {
901 bias-disable;
904 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
905 drive-strength = <12>;
909 sdmmc_clk: sdmmc-clk {
913 sdmmc_cmd: sdmmc-cmd {
917 sdmmc_bus4: sdmmc-bus4 {
926 sdio_clk: sdio-clk {
930 sdio_cmd: sdio-cmd {
934 sdio_bus4: sdio-bus4 {
943 emmc_clk: emmc-clk {
947 emmc_cmd: emmc-cmd {
951 emmc_bus8: emmc-bus8 {
964 rgmii_pins: rgmii-pins {
982 rmii_pins: rmii-pins {
995 phy_pins: phy-pins {
1002 hdmi_hpd: hdmi-hpd {
1006 hdmii2c_xfer: hdmii2c-xfer {
1011 hdmi_cec: hdmi-cec {
1017 i2c0_xfer: i2c0-xfer {
1024 i2c1_xfer: i2c1-xfer {
1031 i2c2_xfer: i2c2-xfer {
1038 i2c3_xfer: i2c3-xfer {
1045 spi0_clk: spi0-clk {
1048 spi0_cs0: spi0-cs0 {
1051 spi0_tx: spi0-tx {
1054 spi0_rx: spi0-rx {
1057 spi0_cs1: spi0-cs1 {
1063 spi1_clk: spi1-clk {
1066 spi1_cs0: spi1-cs0 {
1069 spi1_rx: spi1-rx {
1072 spi1_tx: spi1-tx {
1075 spi1_cs1: spi1-cs1 {
1081 i2s1_bus: i2s1-bus {
1095 pwm0_pin: pwm0-pin {
1099 pwm0_pin_pull_down: pwm0-pin-pull-down {
1105 pwm1_pin: pwm1-pin {
1109 pwm1_pin_pull_down: pwm1-pin-pull-down {
1115 pwm2_pin: pwm2-pin {
1119 pwm2_pin_pull_down: pwm2-pin-pull-down {
1125 pwm3_pin: pwm3-pin {
1129 pwm3_pin_pull_down: pwm3-pin-pull-down {
1135 spdif_tx: spdif-tx {
1141 otp_pin: otp-pin {
1145 otp_out: otp-out {
1151 uart0_xfer: uart0-xfer {
1156 uart0_cts: uart0-cts {
1160 uart0_rts: uart0-rts {
1166 uart1_xfer: uart1-xfer {
1171 uart1_cts: uart1-cts {
1175 uart1_rts: uart1-rts {
1181 uart2_xfer: uart2-xfer {
1186 uart21_xfer: uart21-xfer {
1191 uart2_cts: uart2-cts {
1195 uart2_rts: uart2-rts {