boot/dts/rk322x-android.dtsi

4  * This file is dual-licensed: you can use it either under the terms
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 #include <dt-bindings/pwm/pwm.h>
43 #include <dt-bindings/input/input.h>
50 	fiq-debugger {
51 		compatible = "rockchip,fiq-debugger";
53 		rockchip,serial-id = <2>;
54 		rockchip,signal-irq = <159>;
55 		rockchip,wake-irq = <0>;
56 		rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
58 		pinctrl-names = "default";
59 		pinctrl-0 = <&uart21_xfer>;
66 			compatible = "linaro,optee-tz";
71 	reserved-memory {
72 		#address-cells = <1>;
73 		#size-cells = <1>;
76 		drm_logo: drm-logo@00000000 {
77 			compatible = "rockchip,drm-logo";
81 		secure_memory: secure-memory@80000000 {
82 			compatible = "rockchip,secure-memory";
89 			record-size = <0x20000>;
90 			console-size = <0x80000>;
91 			ftrace-size = <0x00000>;
92 			pmsg-size = <0x50000>;
97 		compatible = "arm,psci-1.0";
103 	enable-method = "psci";
107 	enable-method = "psci";
111 	enable-method = "psci";
115 	enable-method = "psci";
119 	broken-cd;
120 	bus-width = <8>;
121 	cap-mmc-highspeed;
122 	mmc-hs200-1_8v;
123 	no-sdio;
124 	no-sd;
125 	disable-wp;
126 	non-removable;
127 	num-slots = <1>;
128 	/delete-property/ default-sample-phase;
129 	/delete-property/ pinctrl-names;
130 	/delete-property/ pinctrl-0;
143 	bus-width = <4>;
144 	cap-mmc-highspeed;
145 	cap-sd-highspeed;
146 	card-detect-delay = <200>;
147 	disable-wp;
148 	max-frequency = <50000000>;
149 	num-slots = <1>;
150 	no-sdio;
151 	no-mmc;
154 &sdio {
155 	bus-width = <4>;
156 	cap-mmc-highspeed;
157 	cap-sd-highspeed;
158 	cap-sdio-irq;
159 	non-removable;
160 	ignore-pm-notify;
161 	keep-power-in-suspend;
162 	max-frequency = <150000000>;
163 	no-sd;
164 	no-mmc;
168 	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
175 	u2phy0_otg: otg-port {
179 	u2phy0_host: host-port {
187 	u2phy1_otg: otg-port {
191 	u2phy1_host: host-port {
197 	pinctrl-names = "default";
198 	pinctrl-0 = <&uart11_xfer &uart11_cts>;
207 	assigned-clocks = <&cru DCLK_VOP>;
208 	assigned-clock-parents = <&cru HDMIPHY>;