Lines Matching +full:rk3066 +full:- +full:smp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
33 clock-latency = <40000>;
35 operating-points-v2 = <&cpu0_opp_table>;
40 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
43 operating-points-v2 = <&cpu0_opp_table>;
48 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
59 operating-points-v2 = <&cpu0_opp_table>;
65 compatible = "operating-points-v2";
66 opp-shared;
68 opp-312000000 {
69 opp-hz = /bits/ 64 <312000000>;
70 opp-microvolt = <875000>;
71 clock-latency-ns = <40000>;
73 opp-504000000 {
74 opp-hz = /bits/ 64 <504000000>;
75 opp-microvolt = <925000>;
77 opp-600000000 {
78 opp-hz = /bits/ 64 <600000000>;
79 opp-microvolt = <950000>;
80 opp-suspend;
82 opp-816000000 {
83 opp-hz = /bits/ 64 <816000000>;
84 opp-microvolt = <975000>;
86 opp-1008000000 {
87 opp-hz = /bits/ 64 <1008000000>;
88 opp-microvolt = <1075000>;
90 opp-1200000000 {
91 opp-hz = /bits/ 64 <1200000000>;
92 opp-microvolt = <1150000>;
94 opp-1416000000 {
95 opp-hz = /bits/ 64 <1416000000>;
96 opp-microvolt = <1250000>;
98 opp-1608000000 {
99 opp-hz = /bits/ 64 <1608000000>;
100 opp-microvolt = <1350000>;
104 display-subsystem {
105 compatible = "rockchip,display-subsystem";
110 compatible = "mmio-sram";
112 #address-cells = <1>;
113 #size-cells = <1>;
116 smp-sram@0 {
117 compatible = "rockchip,rk3066-smp-sram";
123 compatible = "rockchip,rk3188-vop";
127 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
128 power-domains = <&power RK3188_PD_VIO>;
130 reset-names = "axi", "ahb", "dclk";
134 #address-cells = <1>;
135 #size-cells = <0>;
140 compatible = "rockchip,rk3188-vop";
144 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
145 power-domains = <&power RK3188_PD_VIO>;
147 reset-names = "axi", "ahb", "dclk";
151 #address-cells = <1>;
152 #size-cells = <0>;
157 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
161 clock-names = "pclk", "timer";
165 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
169 clock-names = "pclk", "timer";
173 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
176 pinctrl-names = "default";
177 pinctrl-0 = <&i2s0_bus>;
179 dma-names = "tx", "rx";
180 clock-names = "i2s_hclk", "i2s_clk";
182 rockchip,playback-channels = <2>;
183 rockchip,capture-channels = <2>;
184 #sound-dai-cells = <0>;
189 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
191 #sound-dai-cells = <0>;
193 clock-names = "mclk", "hclk";
195 dma-names = "tx";
197 pinctrl-names = "default";
198 pinctrl-0 = <&spdif_tx>;
202 cru: clock-controller@20000000 {
203 compatible = "rockchip,rk3188-cru";
207 #clock-cells = <1>;
208 #reset-cells = <1>;
212 compatible = "rockchip,rk3188-efuse";
214 #address-cells = <1>;
215 #size-cells = <1>;
217 clock-names = "pclk_efuse";
225 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
227 #address-cells = <1>;
228 #size-cells = <0>;
231 usbphy0: usb-phy@10c {
232 #phy-cells = <0>;
235 clock-names = "phyclk";
236 #clock-cells = <0>;
239 usbphy1: usb-phy@11c {
240 #phy-cells = <0>;
243 clock-names = "phyclk";
244 #clock-cells = <0>;
249 compatible = "rockchip,rk3188-pinctrl";
253 #address-cells = <1>;
254 #size-cells = <1>;
258 compatible = "rockchip,rk3188-gpio-bank0";
261 clock-names = "bus";
264 gpio-controller;
265 #gpio-cells = <2>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
272 compatible = "rockchip,gpio-bank";
275 clock-names = "bus";
278 gpio-controller;
279 #gpio-cells = <2>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
286 compatible = "rockchip,gpio-bank";
289 clock-names = "bus";
292 gpio-controller;
293 #gpio-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
300 compatible = "rockchip,gpio-bank";
303 clock-names = "bus";
306 gpio-controller;
307 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
314 bias-pull-up;
318 bias-pull-down;
322 bias-disable;
326 emmc_clk: emmc-clk {
330 emmc_cmd: emmc-cmd {
334 emmc_rst: emmc-rst {
342 * flash/emmc is the boot-device.
347 emac_xfer: emac-xfer {
358 emac_mdio: emac-mdio {
365 i2c0_xfer: i2c0-xfer {
372 i2c1_xfer: i2c1-xfer {
379 i2c2_xfer: i2c2-xfer {
386 i2c3_xfer: i2c3-xfer {
393 i2c4_xfer: i2c4-xfer {
400 lcdc1_dclk: lcdc1-dclk {
404 lcdc1_den: lcdc1-den {
408 lcdc1_hsync: lcdc1-hsync {
412 lcdc1_vsync: lcdc1-vsync {
416 lcdc1_rgb24: lcdc1-rgb24 {
445 pwm0_out: pwm0-out {
451 pwm1_out: pwm1-out {
457 pwm2_out: pwm2-out {
463 pwm3_out: pwm3-out {
469 spi0_clk: spi0-clk {
472 spi0_cs0: spi0-cs0 {
475 spi0_tx: spi0-tx {
478 spi0_rx: spi0-rx {
481 spi0_cs1: spi0-cs1 {
487 spi1_clk: spi1-clk {
490 spi1_cs0: spi1-cs0 {
493 spi1_rx: spi1-rx {
496 spi1_tx: spi1-tx {
499 spi1_cs1: spi1-cs1 {
505 uart0_xfer: uart0-xfer {
510 uart0_cts: uart0-cts {
514 uart0_rts: uart0-rts {
520 uart1_xfer: uart1-xfer {
525 uart1_cts: uart1-cts {
529 uart1_rts: uart1-rts {
535 uart2_xfer: uart2-xfer {
543 uart3_xfer: uart3-xfer {
548 uart3_cts: uart3-cts {
552 uart3_rts: uart3-rts {
558 sd0_clk: sd0-clk {
562 sd0_cmd: sd0-cmd {
566 sd0_cd: sd0-cd {
570 sd0_wp: sd0-wp {
574 sd0_pwr: sd0-pwr {
578 sd0_bus1: sd0-bus-width1 {
582 sd0_bus4: sd0-bus-width4 {
591 sd1_clk: sd1-clk {
595 sd1_cmd: sd1-cmd {
599 sd1_cd: sd1-cd {
603 sd1_wp: sd1-wp {
607 sd1_bus1: sd1-bus-width1 {
611 sd1_bus4: sd1-bus-width4 {
620 i2s0_bus: i2s0-bus {
631 spdif_tx: spdif-tx {
639 compatible = "rockchip,rk3188-emac";
651 compatible = "rockchip,rk3188-mali", "arm,mali-400";
662 interrupt-names = "gp",
672 power-domains = <&power RK3188_PD_GPU>;
676 compatible = "rockchip,rk3188-i2c";
677 pinctrl-names = "default";
678 pinctrl-0 = <&i2c0_xfer>;
682 compatible = "rockchip,rk3188-i2c";
683 pinctrl-names = "default";
684 pinctrl-0 = <&i2c1_xfer>;
688 compatible = "rockchip,rk3188-i2c";
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c2_xfer>;
694 compatible = "rockchip,rk3188-i2c";
695 pinctrl-names = "default";
696 pinctrl-0 = <&i2c3_xfer>;
700 compatible = "rockchip,rk3188-i2c";
701 pinctrl-names = "default";
702 pinctrl-0 = <&i2c4_xfer>;
706 power: power-controller {
707 compatible = "rockchip,rk3188-power-controller";
708 #power-domain-cells = <1>;
709 #address-cells = <1>;
710 #size-cells = <0>;
712 power-domain@RK3188_PD_VIO {
734 power-domain@RK3188_PD_VIDEO {
743 power-domain@RK3188_PD_GPU {
752 pinctrl-names = "active";
753 pinctrl-0 = <&pwm0_out>;
757 pinctrl-names = "active";
758 pinctrl-0 = <&pwm1_out>;
762 pinctrl-names = "active";
763 pinctrl-0 = <&pwm2_out>;
767 pinctrl-names = "active";
768 pinctrl-0 = <&pwm3_out>;
772 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
773 pinctrl-names = "default";
774 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
778 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
779 pinctrl-names = "default";
780 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
784 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
785 pinctrl-names = "default";
786 pinctrl-0 = <&uart0_xfer>;
790 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
791 pinctrl-names = "default";
792 pinctrl-0 = <&uart1_xfer>;
796 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
797 pinctrl-names = "default";
798 pinctrl-0 = <&uart2_xfer>;
802 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
803 pinctrl-names = "default";
804 pinctrl-0 = <&uart3_xfer>;
808 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";