Lines Matching +full:lvds +full:- +full:decoder
2 * This file is dual-licensed: you can use it either under the terms
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/power/rk3128-power.h>
46 #include <dt-bindings/soc/rockchip,boot-mode.h>
47 #include <dt-bindings/soc/rockchip-system-status.h>
48 #include <dt-bindings/clock/rk3128-cru.h>
49 #include <dt-bindings/display/media-bus-format.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include "rk3128-dram-default-timing.dtsi"
54 interrupt-parent = <&gic>;
55 #address-cells = <1>;
56 #size-cells = <1>;
74 #address-cells = <1>;
75 #size-cells = <0>;
79 compatible = "arm,cortex-a7";
81 operating-points-v2 = <&cpu0_opp_table>;
83 #cooling-cells = <2>; /* min followed by max */
84 dynamic-power-coefficient = <120>;
88 compatible = "arm,cortex-a7";
90 operating-points-v2 = <&cpu0_opp_table>;
94 compatible = "arm,cortex-a7";
96 operating-points-v2 = <&cpu0_opp_table>;
100 compatible = "arm,cortex-a7";
102 operating-points-v2 = <&cpu0_opp_table>;
107 compatible = "operating-points-v2";
108 opp-shared;
110 rockchip,leakage-scaling-sel = <
115 rockchip,leakage-voltage-sel = <
120 nvmem-cells = <&cpu_leakage>;
121 nvmem-cell-names = "cpu_leakage";
123 opp-216000000 {
124 opp-hz = /bits/ 64 <216000000>;
125 opp-microvolt = <1000000 1000000 1425000>;
126 opp-microvolt-L0 = <1000000 1000000 1425000>;
127 opp-microvolt-L1 = <950000 950000 1425000>;
128 opp-microvolt-L2 = <950000 950000 1425000>;
129 clock-latency-ns = <40000>;
131 opp-408000000 {
132 opp-hz = /bits/ 64 <408000000>;
133 opp-microvolt = <1000000 1000000 1425000>;
134 opp-microvolt-L0 = <1000000 1000000 1425000>;
135 opp-microvolt-L1 = <950000 950000 1425000>;
136 opp-microvolt-L2 = <950000 950000 1425000>;
137 clock-latency-ns = <40000>;
139 opp-600000000 {
140 opp-hz = /bits/ 64 <600000000>;
141 opp-microvolt = <1150000 1150000 1425000>;
142 opp-microvolt-L0 = <1150000 1150000 1425000>;
143 opp-microvolt-L1 = <1100000 1100000 1425000>;
144 opp-microvolt-L2 = <1050000 1050000 1425000>;
145 clock-latency-ns = <40000>;
147 opp-696000000 {
148 opp-hz = /bits/ 64 <696000000>;
149 opp-microvolt = <1150000 1150000 1425000>;
150 opp-microvolt-L0 = <1150000 1150000 1425000>;
151 opp-microvolt-L1 = <1100000 1100000 1425000>;
152 opp-microvolt-L2 = <1050000 1050000 1425000>;
153 clock-latency-ns = <40000>;
155 opp-816000000 {
156 opp-hz = /bits/ 64 <816000000>;
157 opp-microvolt = <1200000 1200000 1425000>;
158 opp-microvolt-L0 = <1200000 1200000 1425000>;
159 opp-microvolt-L1 = <1150000 1150000 1425000>;
160 opp-microvolt-L2 = <1100000 1100000 1425000>;
161 clock-latency-ns = <40000>;
162 opp-suspend;
164 opp-1008000000 {
165 opp-hz = /bits/ 64 <1008000000>;
166 opp-microvolt = <1350000 1350000 1425000>;
167 opp-microvolt-L0 = <1350000 1350000 1425000>;
168 opp-microvolt-L1 = <1275000 1275000 1425000>;
169 opp-microvolt-L2 = <1225000 1225000 1425000>;
170 clock-latency-ns = <40000>;
172 opp-1200000000 {
173 opp-hz = /bits/ 64 <1200000000>;
174 opp-microvolt = <1425000 1425000 1425000>;
175 opp-microvolt-L0 = <1425000 1425000 1425000>;
176 opp-microvolt-L1 = <1425000 1425000 1425000>;
177 opp-microvolt-L2 = <1375000 1375000 1425000>;
178 clock-latency-ns = <40000>;
183 compatible = "simple-bus";
184 #address-cells = <1>;
185 #size-cells = <1>;
193 #dma-cells = <1>;
194 arm,pl330-broken-no-flushp;
195 arm,pl330-periph-burst;
197 clock-names = "apb_pclk";
201 arm-pmu {
202 compatible = "arm,cortex-a7-pmu";
207 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
211 compatible = "rockchip,rk3128-dfi";
217 display_subsystem: display-subsystem {
218 compatible = "rockchip,display-subsystem";
224 compatible = "rockchip,rk3128-dmc";
225 devfreq-events = <&dfi>;
227 clock-names = "dmc_clk";
230 operating-points-v2 = <&dmc_opp_table>;
231 vop-dclk-mode = <0>;
232 min-cpu-freq = <600000>;
234 system-status-freq = <
240 auto-min-freq = <456000>;
241 auto-freq-en = <0>;
246 compatible = "operating-points-v2";
248 opp-200000000 {
249 opp-hz = /bits/ 64 <200000000>;
250 opp-microvolt = <1025000>;
253 opp-300000000 {
254 opp-hz = /bits/ 64 <300000000>;
255 opp-microvolt = <1025000>;
257 opp-396000000 {
258 opp-hz = /bits/ 64 <396000000>;
259 opp-microvolt = <1100000>;
261 opp-456000000 {
262 opp-hz = /bits/ 64 <456000000>;
263 opp-microvolt = <1200000>;
269 compatible = "linaro,optee-tz";
276 compatible = "arm,psci-1.0";
281 compatible = "arm,armv7-timer";
286 clock-frequency = <24000000>;
289 thermal-zones {
290 soc_thermal: soc-thermal {
291 polling-delay-passive = <1000>;
292 polling-delay = <2000>;
293 sustainable-power = <200>;
295 thermal-sensors = <&tsadc 0>;
298 threshold: trip-point0 {
303 target: trip-point1 {
310 cooling-maps {
313 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
318 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
327 compatible = "rockchip,rk3126-tsadc-virtual";
328 nvmem-cells = <&cpu_leakage>;
329 nvmem-cell-names = "cpu_leakage";
330 #thermal-sensor-cells = <1>;
335 compatible = "fixed-clock";
336 clock-frequency = <24000000>;
337 clock-output-names = "xin24m";
338 #clock-cells = <0>;
354 interrupt-names = "Mali_GP_IRQ",
361 #cooling-cells = <2>; /* min followed by max */
362 clock-names = "clk_mali";
363 power-domains = <&power RK3128_PD_GPU>;
364 operating-points-v2 = <&gpu_opp_table>;
368 compatible = "arm,mali-simple-power-model";
371 static-power = <300>;
372 dynamic-power = <396>;
373 ts = <32000 4700 (-80) 2>;
374 thermal-zone = "soc-thermal";
378 gpu_opp_table: opp-table2 {
379 compatible = "operating-points-v2";
381 opp-200000000 {
382 opp-hz = /bits/ 64 <200000000>;
383 opp-microvolt = <975000>;
385 opp-300000000 {
386 opp-hz = /bits/ 64 <300000000>;
387 opp-microvolt = <1050000>;
389 opp-400000000 {
390 opp-hz = /bits/ 64 <400000000>;
391 opp-microvolt = <1150000>;
393 opp-480000000 {
394 opp-hz = /bits/ 64 <480000000>;
395 opp-microvolt = <1250000>;
400 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
402 #address-cells = <1>;
403 #size-cells = <1>;
405 power: power-controller {
406 compatible = "rockchip,rk3128-power-controller";
407 #power-domain-cells = <1>;
408 #address-cells = <1>;
409 #size-cells = <0>;
453 reboot_mode: reboot-mode {
454 compatible = "syscon-reboot-mode";
456 mode-bootloader = <BOOT_BL_DOWNLOAD>;
457 mode-charge = <BOOT_CHARGING>;
458 mode-fastboot = <BOOT_FASTBOOT>;
459 mode-loader = <BOOT_BL_DOWNLOAD>;
460 mode-normal = <BOOT_NORMAL>;
461 mode-recovery = <BOOT_RECOVERY>;
462 mode-ums = <BOOT_UMS>;
466 mpp_srv: mpp-srv {
467 compatible = "rockchip,mpp-service";
468 rockchip,taskqueue-count = <1>;
469 rockchip,resetgroup-count = <1>;
471 rockchip,grf-offset = <0x0144>;
472 rockchip,grf-values = <0x04000400>, <0x04000400>;
473 rockchip,grf-names = "grf_vdpu1", "grf_vepu1";
478 compatible = "rockchip,hevc-decoder";
481 interrupt-names = "irq_dec";
484 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
487 reset-names = "shared_video_h", "shared_video_a",
490 power-domains = <&power RK3128_PD_VIDEO>;
492 rockchip,taskqueue-node = <0>;
493 rockchip,resetgroup-node = <0>;
501 interrupt-names = "hevc_mmu";
502 clock-names = "aclk", "iface";
504 power-domains = <&power RK3128_PD_VIDEO>;
505 #iommu-cells = <0>;
510 compatible = "rockchip,vpu-encoder-v1";
513 interrupt-names = "irq_enc";
515 clock-names = "aclk_vcodec", "hclk_vcodec";
517 reset-names = "shared_video_h", "shared_video_a";
519 power-domains = <&power RK3128_PD_VIDEO>;
521 rockchip,taskqueue-node = <0>;
522 rockchip,resetgroup-node = <0>;
527 compatible = "rockchip,vpu-decoder-v1";
530 interrupt-names = "irq_dec";
532 clock-names = "aclk_vcodec", "hclk_vcodec";
534 reset-names = "shared_video_h", "shared_video_a";
536 power-domains = <&power RK3128_PD_VIDEO>;
538 rockchip,taskqueue-node = <0>;
539 rockchip,resetgroup-node = <0>;
547 interrupt-names = "vpu_mmu";
549 clock-names = "aclk", "iface";
550 power-domains = <&power RK3128_PD_VIDEO>;
551 #iommu-cells = <0>;
562 clock-names = "aclk_iep", "hclk_iep";
563 power-domains = <&power RK3128_PD_VIO>;
573 interrupt-names = "iep_mmu";
575 clock-names = "aclk", "iface";
576 power-domains = <&power RK3128_PD_VIO>;
577 #iommu-cells = <0>;
587 clock-names = "aclk_cif0", "hclk_cif0",
590 reset-names = "rst_cif";
591 power-domains = <&power RK3128_PD_VIO>;
595 cif_new: cif-new@1010a000 {
596 compatible = "rockchip,rk3128-cif";
601 clock-names = "aclk_cif", "hclk_cif",
604 reset-names = "rst_cif";
608 power-domains = <&power RK3128_PD_VIO>;
614 compatible = "rockchip,rk312x-rga";
618 clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
619 power-domains = <&power RK3128_PD_VIO>;
624 compatible = "rockchip,rk3126-vop";
626 reg-names = "regs", "gamma_lut";
629 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
631 reset-names = "axi", "ahb", "dclk";
633 power-domains = <&power RK3128_PD_VIO>;
637 #address-cells = <1>;
638 #size-cells = <0>;
642 remote-endpoint = <&dsi_in_vop>;
647 remote-endpoint = <&lvds_in_vop>;
652 remote-endpoint = <&rgb_in_vop>;
661 interrupt-names = "vop_mmu";
663 clock-names = "aclk", "iface";
664 power-domains = <&power RK3128_PD_VIO>;
665 #iommu-cells = <0>;
666 rockchip,disable-device-link-resume;
671 compatible = "rockchip,rk3128-mipi-dsi";
675 clock-names = "pclk", "hclk";
677 reset-names = "apb";
679 phy-names = "dphy";
680 power-domains = <&power RK3128_PD_VIO>;
682 #address-cells = <1>;
683 #size-cells = <0>;
689 remote-endpoint = <&vop_out_dsi>;
725 gic: interrupt-controller@10139000 {
726 compatible = "arm,cortex-a7-gic";
727 interrupt-controller;
728 #interrupt-cells = <3>;
729 #address-cells = <0>;
739 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb",
744 clock-names = "otg";
746 g-np-tx-fifo-size = <16>;
747 g-rx-fifo-size = <280>;
748 g-tx-fifo-size = <256 128 128 64 32 16>;
749 g-use-dma;
751 phy-names = "usb2-phy";
756 compatible = "generic-ehci";
760 clock-names = "usbhost", "utmi";
762 phy-names = "usb";
767 compatible = "generic-ohci";
771 clock-names = "usbhost", "utmi";
773 phy-names = "usb";
777 i2s_8ch: i2s-8ch@10200000 {
778 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
781 clock-names = "i2s_clk", "i2s_hclk";
784 dma-names = "tx", "rx";
786 reset-names = "reset-m";
791 compatible = "rockchip,rk3128-spdif";
795 clock-names = "mclk", "hclk";
797 dma-names = "tx";
798 pinctrl-names = "default";
799 pinctrl-0 = <&spdif_tx>;
808 clock-names = "clk_sfc", "hclk_sfc";
809 assigned-clocks = <&cru SCLK_SFC>;
810 assigned-clock-rates = <60000000>;
814 i2s_2ch: i2s-2ch@10220000 {
815 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
818 clock-names = "i2s_clk", "i2s_hclk";
821 dma-names = "tx", "rx";
823 reset-names = "reset-m";
828 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
831 #address-cells = <1>;
832 #size-cells = <0>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
835 max-frequency = <50000000>;
837 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
839 dma-names = "rx-tx";
840 fifo-depth = <0x100>;
841 bus-width = <4>;
846 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
849 #address-cells = <1>;
850 #size-cells = <0>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&sdio_pwren &sdio_cmd &sdio_clk &sdio_bus4>;
853 clock-freq-min-max = <400000 50000000>;
855 clock-names = "biu", "ciu";
857 dma-names = "rx-tx";
858 num-slots = <1>;
859 fifo-depth = <0x100>;
860 bus-width = <4>;
865 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
868 #address-cells = <1>;
869 #size-cells = <0>;
870 clock-freq-min-max = <400000 50000000>;
872 clock-names = "biu", "ciu";
874 dma-names = "rx-tx";
875 num-slots = <1>;
876 fifo-depth = <0x100>;
877 bus-width = <8>;
882 compatible = "rockchip,rk-nandc";
887 clock-names = "clk_nandc", "hclk_nandc";
891 cru: clock-controller@20000000 {
892 compatible = "rockchip,rk3128-cru";
895 #clock-cells = <1>;
896 #reset-cells = <1>;
897 assigned-clocks = <&cru PLL_GPLL>,
901 assigned-clock-rates = <594000000>,
908 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
910 #address-cells = <1>;
911 #size-cells = <1>;
913 lvds: lvds { label
914 compatible = "rockchip,rk3126-lvds";
916 phy-names = "phy";
920 #address-cells = <1>;
921 #size-cells = <0>;
927 remote-endpoint = <&vop_out_lvds>;
934 compatible = "rockchip,rk3128-rgb";
936 phy-names = "phy";
937 pinctrl-names = "default", "sleep";
938 pinctrl-0 = <&lcdc_rgb_pins>;
939 pinctrl-1 = <&lcdc_sleep_pins>;
943 #address-cells = <1>;
944 #size-cells = <0>;
950 remote-endpoint = <&vop_out_rgb>;
956 u2phy: usb2-phy@17c {
957 compatible = "rockchip,rk3128-usb2phy";
960 clock-names = "phyclk";
961 #clock-cells = <0>;
962 clock-output-names = "usb480m_phy";
963 assigned-clocks = <&cru SCLK_USB480M>;
964 assigned-clock-parents = <&u2phy>;
967 u2phy_otg: otg-port {
968 #phy-cells = <0>;
972 interrupt-names = "otg-bvalid", "otg-id",
977 u2phy_host: host-port {
978 #phy-cells = <0>;
980 interrupt-names = "linestate";
987 compatible = "rockchip,rk3128-codec";
994 clock-names = "g_pclk_acodec", "i2s_clk";
998 video_phy: video-phy@20038000 {
999 compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy";
1001 reg-names = "phy", "host";
1004 clock-names = "ref", "pclk", "pclk_host";
1005 #clock-cells = <0>;
1007 reset-names = "apb";
1008 power-domains = <&power RK3128_PD_VIO>;
1009 #phy-cells = <0>;
1014 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
1018 clock-names = "timer", "pclk";
1022 compatible = "snps,dw-wdt";
1030 compatible = "rockchip,rk3288-pwm";
1032 #pwm-cells = <3>;
1033 pinctrl-names = "active";
1034 pinctrl-0 = <&pwm0_pin>;
1036 clock-names = "pwm";
1041 compatible = "rockchip,rk3288-pwm";
1043 #pwm-cells = <3>;
1044 pinctrl-names = "active";
1045 pinctrl-0 = <&pwm1_pin>;
1047 clock-names = "pwm";
1052 compatible = "rockchip,rk3288-pwm";
1054 #pwm-cells = <3>;
1055 pinctrl-names = "active";
1056 pinctrl-0 = <&pwm2_pin>;
1058 clock-names = "pwm";
1063 compatible = "rockchip,rk3288-pwm";
1065 #pwm-cells = <3>;
1066 pinctrl-names = "active";
1067 pinctrl-0 = <&pwm3_pin>;
1069 clock-names = "pwm";
1074 compatible = "rockchip,rk3288-i2c";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 clock-names = "i2c";
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&i2c1_xfer>;
1087 compatible = "rockchip,rk3288-i2c";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 clock-names = "i2c";
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&i2c2_xfer>;
1100 compatible = "rockchip,rk3288-i2c";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 clock-names = "i2c";
1107 pinctrl-names = "default";
1108 pinctrl-0 = <&i2c3_xfer>;
1113 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
1116 clock-frequency = <24000000>;
1118 clock-names = "baudclk", "apb_pclk";
1119 reg-shift = <2>;
1120 reg-io-width = <4>;
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
1127 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
1130 clock-frequency = <24000000>;
1132 clock-names = "baudclk", "apb_pclk";
1133 reg-shift = <2>;
1134 reg-io-width = <4>;
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
1141 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
1144 clock-frequency = <24000000>;
1146 clock-names = "baudclk", "apb_pclk";
1147 reg-shift = <2>;
1148 reg-io-width = <4>;
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&uart2_xfer>;
1158 #io-channel-cells = <1>;
1160 clock-names = "saradc", "apb_pclk";
1162 reset-names = "saradc-apb";
1167 compatible = "rockchip,rk3288-i2c";
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 clock-names = "i2c";
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&i2c0_xfer>;
1180 compatible = "rockchip,rk3288-spi";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>;
1185 clock-names = "spiclk", "apb_pclk";
1187 dma-names = "tx", "rx";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1194 compatible = "rockchip,rk3128-gmac";
1198 interrupt-names = "macirq", "eth_wake_irq";
1204 clock-names = "stmmaceth",
1209 reset-names = "stmmaceth";
1214 compatible = "rockchip,rk3128-efuse";
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1219 clock-names = "pclk_efuse";
1229 rockchip_system_monitor: rockchip-system-monitor {
1230 compatible = "rockchip,system-monitor";
1234 compatible = "rockchip,rk3128-pinctrl";
1236 #address-cells = <1>;
1237 #size-cells = <1>;
1241 compatible = "rockchip,gpio-bank";
1246 gpio-controller;
1247 #gpio-cells = <2>;
1249 interrupt-controller;
1250 #interrupt-cells = <2>;
1254 compatible = "rockchip,gpio-bank";
1259 gpio-controller;
1260 #gpio-cells = <2>;
1262 interrupt-controller;
1263 #interrupt-cells = <2>;
1267 compatible = "rockchip,gpio-bank";
1272 gpio-controller;
1273 #gpio-cells = <2>;
1275 interrupt-controller;
1276 #interrupt-cells = <2>;
1280 compatible = "rockchip,gpio-bank";
1285 gpio-controller;
1286 #gpio-cells = <2>;
1288 interrupt-controller;
1289 #interrupt-cells = <2>;
1293 bias-pull-pin-default;
1296 pcfg_output_high: pcfg-output-high {
1297 output-high;
1300 pcfg_pull_none: pcfg-pull-none {
1301 bias-disable;
1305 emmc_clk: emmc-clk {
1309 emmc_cmd: emmc-cmd {
1313 emmc_cmd1: emmc-cmd1 {
1317 emmc_pwr: emmc-pwr {
1321 emmc_bus1: emmc-bus1 {
1325 emmc_bus4: emmc-bus4 {
1332 emmc_bus8: emmc-bus8 {
1345 i2c0_xfer: i2c0-xfer {
1352 i2c1_xfer: i2c1-xfer {
1359 i2c2_xfer: i2c2-xfer {
1366 i2c3_xfer: i2c3-xfer {
1373 lcdc_rgb_pins: lcdc-rgb-pins {
1395 lcdc_sleep_pins: lcdc-sleep-pins {
1419 uart0_xfer: uart0-xfer {
1424 uart0_cts: uart0-cts {
1428 uart0_rts: uart0-rts {
1434 uart1_xfer: uart1-xfer {
1439 uart1_cts: uart1-cts {
1443 uart1_rts: uart1-rts {
1449 uart2_xfer: uart2-xfer {
1454 uart2_cts: uart2-cts {
1458 uart2_rts: uart2-rts {
1464 sdmmc_clk: sdmmc-clk {
1468 sdmmc_det: sdmmc-det {
1472 sdmmc_cmd: sdmmc-cmd {
1476 sdmmc_wp: sdmmc-wp {
1480 sdmmc_pwren: sdmmc-pwren {
1484 sdmmc_bus4: sdmmc-bus4 {
1493 sdio_clk: sdio-clk {
1497 sdio_cmd: sdio-cmd {
1501 sdio_pwren: sdio-pwren {
1505 sdio_bus4: sdio-bus4 {
1514 hdmii2c_xfer: hdmii2c-xfer {
1519 hdmi_hpd: hdmi-hpd {
1523 hdmi_cec: hdmi-cec {
1529 i2s_bus: i2s-bus {
1538 i2s1_bus: i2s1-bus {
1549 pwm0_pin: pwm0-pin {
1555 pwm1_pin: pwm1-pin {
1561 pwm2_pin: pwm2-pin {
1567 pwm3_pin: pwm3-pin {
1573 rgmii_pins: rgmii-pins {
1591 rmii_pins: rmii-pins {
1606 spdif_tx: spdif-tx {
1612 spi0m0_clk: spi0m0-clk {
1616 spi0m0_cs0: spi0m0-cs0 {
1620 spi0m0_tx: spi0m0-tx {
1624 spi0m0_rx: spi0m0-rx {
1628 spi0m0_cs1: spi0m0-cs1 {
1632 spi0m1_clk: spi0m1-clk {
1636 spi0m1_cs0: spi0m1-cs0 {
1640 spi0m1_tx: spi0m1-tx {
1644 spi0m1_rx: spi0m1-rx {
1648 spi0m1_cs1: spi0m1-cs1 {
1652 spi0m2_clk: spi0m2-clk {
1656 spi0m2_cs0: spi0m2-cs0 {
1660 spi0m2_tx: spi0m2-tx {
1664 spi0m2_rx: spi0m2-rx {