Lines Matching +full:sclk +full:- +full:strength
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3228-cru.h>
12 #include <dt-bindings/power/rk3228-power.h>
13 #include <dt-bindings/suspend/rockchip-rk322x.h>
14 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include <dt-bindings/soc/rockchip-system-status.h>
17 #include "rk322x-dram-default-timing.dtsi"
21 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a7";
38 enable-method = "psci";
40 operating-points-v2 = <&cpu0_opp_table>;
41 #cooling-cells = <2>; /* min followed by max */
42 dynamic-power-coefficient = <122>;
43 clock-latency = <40000>;
49 compatible = "arm,cortex-a7";
51 enable-method = "psci";
53 operating-points-v2 = <&cpu0_opp_table>;
58 compatible = "arm,cortex-a7";
60 enable-method = "psci";
62 operating-points-v2 = <&cpu0_opp_table>;
67 compatible = "arm,cortex-a7";
69 enable-method = "psci";
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "operating-points-v2";
77 opp-shared;
80 rockchip,leakage-scaling-sel = <
84 rockchip,max-volt = <1350000>;
85 rockchip,leakage-voltage-sel = <
89 nvmem-cells = <&cpu_leakage>;
90 nvmem-cell-names = "cpu_leakage";
92 opp-408000000 {
93 opp-hz = /bits/ 64 <408000000>;
94 opp-microvolt = <950000 950000 1200000>;
95 opp-microvolt-L0 = <950000 950000 1200000>;
96 opp-microvolt-L1 = <950000 950000 1200000>;
97 clock-latency-ns = <40000>;
98 opp-suspend;
100 opp-600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <975000 975000 1200000>;
103 opp-microvolt-L0 = <975000 975000 1200000>;
104 opp-microvolt-L1 = <975000 975000 1200000>;
106 opp-816000000 {
107 opp-hz = /bits/ 64 <816000000>;
108 opp-microvolt = <1000000 1000000 1200000>;
109 opp-microvolt-L0 = <1000000 1000000 1200000>;
110 opp-microvolt-L1 = <1000000 1000000 1200000>;
112 opp-1008000000 {
113 opp-hz = /bits/ 64 <1008000000>;
114 opp-microvolt = <1175000 1175000 1200000>;
115 opp-microvolt-L0 = <1175000 1175000 1200000>;
116 opp-microvolt-L1 = <1125000 1125000 1200000>;
118 opp-1200000000 {
119 opp-hz = /bits/ 64 <1200000000>;
120 opp-microvolt = <1175000 1175000 1200000>;
121 opp-microvolt-L0 = <1175000 1175000 1200000>;
122 opp-microvolt-L1 = <1125000 1125000 1200000>;
127 compatible = "arm,amba-bus";
128 #address-cells = <1>;
129 #size-cells = <1>;
137 #dma-cells = <1>;
139 clock-names = "apb_pclk";
140 arm,pl330-periph-burst;
144 arm-pmu {
145 compatible = "arm,cortex-a7-pmu";
150 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
156 clock-names = "dmc_clk";
157 operating-points-v2 = <&dmc_opp_table>;
158 system-status-freq = <
164 #cooling-cells = <2>;
169 dynamic-power-coefficient = <120>;
170 static-power-coefficient = <200>;
171 ts = <32000 4700 (-80) 2>;
172 thermal-zone = "soc-thermal";
176 dmc_opp_table: dmc-opp-table {
177 compatible = "operating-points-v2";
179 rockchip,leakage-voltage-sel = <
183 nvmem-cells = <&logic_leakage>;
184 nvmem-cell-names = "ddr_leakage";
186 opp-300000000 {
187 opp-hz = /bits/ 64 <300000000>;
188 opp-microvolt = <1050000>;
189 opp-microvolt-L0 = <1050000>;
190 opp-microvolt-L1 = <1000000>;
192 opp-330000000 {
193 opp-hz = /bits/ 64 <330000000>;
194 opp-microvolt = <1050000>;
195 opp-microvolt-L0 = <1050000>;
196 opp-microvolt-L1 = <1000000>;
198 opp-400000000 {
199 opp-hz = /bits/ 64 <400000000>;
200 opp-microvolt = <1050000>;
201 opp-microvolt-L0 = <1050000>;
202 opp-microvolt-L1 = <1000000>;
205 opp-600000000 {
206 opp-hz = /bits/ 64 <600000000>;
207 opp-microvolt = <1100000>;
208 opp-microvolt-L0 = <1100000>;
209 opp-microvolt-L1 = <1050000>;
212 opp-666000000 {
213 opp-hz = /bits/ 64 <666000000>;
214 opp-microvolt = <1150000>;
215 opp-microvolt-L0 = <1150000>;
216 opp-microvolt-L1 = <1100000>;
219 opp-700000000 {
220 opp-hz = /bits/ 64 <700000000>;
221 opp-microvolt = <1150000>;
222 opp-microvolt-L0 = <1150000>;
223 opp-microvolt-L1 = <1100000>;
226 opp-786000000 {
227 opp-hz = /bits/ 64 <786000000>;
228 opp-microvolt = <1150000>;
229 opp-microvolt-L0 = <1150000>;
230 opp-microvolt-L1 = <1100000>;
233 opp-800000000 {
234 opp-hz = /bits/ 64 <800000000>;
235 opp-microvolt = <1150000>;
236 opp-microvolt-L0 = <1150000>;
237 opp-microvolt-L1 = <1100000>;
244 compatible = "linaro,optee-tz";
250 compatible = "arm,armv7-timer";
255 clock-frequency = <24000000>;
259 compatible = "fixed-clock";
260 clock-frequency = <24000000>;
261 clock-output-names = "xin24m";
262 #clock-cells = <0>;
266 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clock-names = "i2s_clk", "i2s_hclk";
274 dma-names = "tx", "rx";
275 pinctrl-names = "default";
276 pinctrl-0 = <&i2s1_bus>;
281 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 clock-names = "i2s_clk", "i2s_hclk";
289 dma-names = "tx", "rx";
294 compatible = "rockchip,rk3228-spdif";
298 clock-names = "mclk", "hclk";
300 #dma-cells = <1>;
301 dma-names = "tx";
302 pinctrl-names = "default";
303 pinctrl-0 = <&spdif_tx>;
308 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 clock-names = "i2s_clk", "i2s_hclk";
316 dma-names = "tx", "rx";
321 compatible = "rockchip,rk3228-tsp";
324 interrupt-names = "irq_tsp";
326 clock-names = "clk_tsp", "hclk_tsp", "aclk_tsp";
327 pinctrl-names = "default";
328 pinctrl-0 = <&tsp_d0
344 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
346 #address-cells = <1>;
347 #size-cells = <1>;
349 io_domains: io-domains {
350 compatible = "rockchip,rk322x-io-voltage-domain";
354 reboot_mode: reboot-mode {
355 compatible = "syscon-reboot-mode";
357 mode-normal = <BOOT_NORMAL>;
358 mode-recovery = <BOOT_RECOVERY>;
359 mode-bootloader = <BOOT_FASTBOOT>;
360 mode-loader = <BOOT_BL_DOWNLOAD>;
361 mode-ums = <BOOT_UMS>;
364 u2phy0: usb2-phy@760 {
365 compatible = "rockchip,rk3228-usb2phy";
368 clock-names = "phyclk";
369 #clock-cells = <0>;
370 clock-output-names = "usb480m_phy0";
373 u2phy0_otg: otg-port {
374 #phy-cells = <0>;
378 interrupt-names = "otg-bvalid", "otg-id",
383 u2phy0_host: host-port {
384 #phy-cells = <0>;
386 interrupt-names = "linestate";
391 u2phy1: usb2-phy@800 {
392 compatible = "rockchip,rk3228-usb2phy";
395 clock-names = "phyclk";
396 #clock-cells = <0>;
397 clock-output-names = "usb480m_phy1";
400 u2phy1_otg: otg-port {
401 #phy-cells = <0>;
403 interrupt-names = "linestate";
407 u2phy1_host: host-port {
408 #phy-cells = <0>;
410 interrupt-names = "linestate";
415 power: power-controller {
416 compatible = "rockchip,rk3228-power-controller";
417 #power-domain-cells = <1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
440 compatible = "snps,dw-apb-uart";
443 clock-frequency = <24000000>;
445 clock-names = "baudclk", "apb_pclk";
446 pinctrl-names = "default";
447 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
448 reg-shift = <2>;
449 reg-io-width = <4>;
454 compatible = "snps,dw-apb-uart";
457 clock-frequency = <24000000>;
459 clock-names = "baudclk", "apb_pclk";
460 pinctrl-names = "default";
461 pinctrl-0 = <&uart1_xfer>;
462 reg-shift = <2>;
463 reg-io-width = <4>;
468 compatible = "snps,dw-apb-uart";
471 clock-frequency = <24000000>;
473 clock-names = "baudclk", "apb_pclk";
474 pinctrl-names = "default";
475 pinctrl-0 = <&uart21_xfer>;
476 reg-shift = <2>;
477 reg-io-width = <4>;
482 compatible = "rockchip,rk322x-efuse";
484 #address-cells = <1>;
485 #size-cells = <1>;
487 clock-names = "pclk_efuse";
496 logic_leakage: logic-leakage@19 {
510 compatible = "rockchip,rk3228-i2c";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 clock-names = "i2c";
517 pinctrl-names = "default";
518 pinctrl-0 = <&i2c0_xfer>;
523 compatible = "rockchip,rk3228-i2c";
526 #address-cells = <1>;
527 #size-cells = <0>;
528 clock-names = "i2c";
530 pinctrl-names = "default";
531 pinctrl-0 = <&i2c1_xfer>;
536 compatible = "rockchip,rk3228-i2c";
539 #address-cells = <1>;
540 #size-cells = <0>;
541 clock-names = "i2c";
543 pinctrl-names = "default";
544 pinctrl-0 = <&i2c2_xfer>;
549 compatible = "rockchip,rk3228-i2c";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 clock-names = "i2c";
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c3_xfer>;
562 compatible = "rockchip,rk3228-spi";
565 #address-cells = <1>;
566 #size-cells = <0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
570 clock-names = "spiclk", "apb_pclk";
575 compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
583 compatible = "rockchip,rk3288-pwm";
585 #pwm-cells = <3>;
587 clock-names = "pwm";
588 pinctrl-names = "active";
589 pinctrl-0 = <&pwm0_pin>;
594 compatible = "rockchip,rk3288-pwm";
596 #pwm-cells = <3>;
598 clock-names = "pwm";
599 pinctrl-names = "active";
600 pinctrl-0 = <&pwm1_pin>;
605 compatible = "rockchip,rk3288-pwm";
607 #pwm-cells = <3>;
609 clock-names = "pwm";
610 pinctrl-names = "active";
611 pinctrl-0 = <&pwm2_pin>;
616 compatible = "rockchip,rk3288-pwm";
619 #pwm-cells = <3>;
621 clock-names = "pwm";
622 pinctrl-names = "active";
623 pinctrl-0 = <&pwm3_pin>;
628 compatible = "rockchip,rk3288-timer";
632 clock-names = "timer", "pclk";
635 cru: clock-controller@110e0000 {
636 compatible = "rockchip,rk3228-cru";
639 #clock-cells = <1>;
640 #reset-cells = <1>;
641 assigned-clocks =
647 assigned-clock-rates =
655 thermal_zones: thermal-zones {
656 soc_thermal: soc-thermal {
657 polling-delay-passive = <100>; /* milliseconds */
658 polling-delay = <5000>; /* milliseconds */
659 sustainable-power = <1200>; /* milliwatts */
661 thermal-sensors = <&tsadc 0>;
664 threshold: trip-point@0 {
669 target: trip-point@1 {
674 soc_crit: soc-crit {
681 cooling-maps {
684 cooling-device =
690 cooling-device =
696 cooling-device =
702 cooling-device =
711 compatible = "rockchip,rk3228-tsadc";
715 clock-names = "tsadc", "apb_pclk";
716 assigned-clocks = <&cru SCLK_TSADC>;
717 assigned-clock-rates = <32768>;
719 reset-names = "tsadc-apb";
720 pinctrl-names = "gpio", "otpout";
721 pinctrl-0 = <&otp_gpio>;
722 pinctrl-1 = <&otp_out>;
723 #thermal-sensor-cells = <0>;
724 rockchip,hw-tshut-temp = <120000>;
729 compatible = "rockchip,rk3228-codec";
732 clock-names = "mclk", "pclk", "sclk";
733 spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
737 hdmi_phy: hdmi-phy@12030000 {
738 compatible = "rockchip,rk3228-hdmi-phy";
740 #phy-cells = <0>;
742 clock-names = "sysclk", "refclk";
743 #clock-cells = <0>;
744 clock-output-names = "hdmiphy_phy";
745 nvmem-cells = <&hdmi_phy_flag>;
746 nvmem-cell-names = "hdmi_phy_flag";
747 rockchip,phy-table =
763 reg-names = "Mali_L2",
778 interrupt-names = "Mali_GP_IRQ",
785 #cooling-cells = <2>; /* min followed by max */
786 clock-names = "clk_mali";
787 operating-points-v2 = <&gpu_opp_table>;
791 compatible = "arm,mali-simple-power-model";
794 static-power = <300>;
795 dynamic-power = <396>;
796 ts = <32000 4700 (-80) 2>;
797 thermal-zone = "soc-thermal";
801 gpu_opp_table: opp-table2 {
802 compatible = "operating-points-v2";
804 rockchip,leakage-voltage-sel = <
808 nvmem-cells = <&logic_leakage>;
809 nvmem-cell-names = "gpu_leakage";
811 opp-200000000 {
812 opp-hz = /bits/ 64 <200000000>;
813 opp-microvolt = <1050000>;
814 opp-microvolt-L0 = <1050000>;
815 opp-microvolt-L1 = <1000000>;
817 opp-300000000 {
818 opp-hz = /bits/ 64 <300000000>;
819 opp-microvolt = <1050000>;
820 opp-microvolt-L0 = <1050000>;
821 opp-microvolt-L1 = <1000000>;
823 opp-400000000 {
824 opp-hz = /bits/ 64 <400000000>;
825 opp-microvolt = <1125000>;
826 opp-microvolt-L0 = <1125000>;
827 opp-microvolt-L1 = <1100000>;
831 vpu_service: vpu-service@20020000 {
836 interrupt-names = "irq_dec", "irq_enc";
838 reset-names = "video_a", "video_h";
840 clock-names = "aclk_vcodec", "hclk_vcodec";
841 power-domains = <&power RK3228_PD_VPU>;
852 interrupt-names = "vpu_mmu";
853 clock-names = "aclk", "iface";
855 power-domains = <&power RK3228_PD_VPU>;
856 #iommu-cells = <0>;
864 interrupt-names = "irq_dec";
867 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac",
872 reset-names = "video_a", "video_h", "niu_a", "niu_h",
874 power-domains = <&power RK3228_PD_RKVDEC>;
875 operating-points-v2 = <&rkvdec_opp_table>;
876 #cooling-cells = <2>;
884 dynamic-power-coefficient = <120>;
885 static-power-coefficient = <200>;
886 ts = <32000 4700 (-80) 2>;
887 thermal-zone = "soc-thermal";
891 rkvdec_opp_table: rkvdec-opp-table {
892 compatible = "operating-points-v2";
894 rockchip,leakage-voltage-sel = <
898 nvmem-cells = <&logic_leakage>;
899 nvmem-cell-names = "rkvdec_leakage";
901 opp-100000000 {
902 opp-hz = /bits/ 64 <100000000>;
903 opp-microvolt = <1050000>;
904 opp-microvolt-L0 = <1050000>;
905 opp-microvolt-L1 = <1000000>;
907 opp-200000000 {
908 opp-hz = /bits/ 64 <200000000>;
909 opp-microvolt = <1050000>;
910 opp-microvolt-L0 = <1050000>;
911 opp-microvolt-L1 = <1000000>;
913 opp-500000000 {
914 opp-hz = /bits/ 64 <500000000>;
915 opp-microvolt = <1050000>;
916 opp-microvolt-L0 = <1050000>;
917 opp-microvolt-L1 = <1000000>;
925 interrupt-names = "rkvdec_mmu";
927 clock-names = "aclk", "iface";
928 power-domains = <&power RK3228_PD_RKVDEC>;
929 #iommu-cells = <0>;
934 compatible = "rockchip,rk322x-vop";
936 reg-names = "regs";
939 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
941 reset-names = "axi", "ahb", "dclk";
946 #address-cells = <1>;
947 #size-cells = <0>;
951 remote-endpoint = <&hdmi_in_vop>;
956 remote-endpoint = <&tve_in_vop>;
965 interrupt-names = "vop_mmu";
967 clock-names = "aclk", "iface";
968 #iommu-cells = <0>;
977 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
978 dma-coherent;
989 clock-names = "aclk_iep", "hclk_iep";
999 interrupt-names = "iep_mmu";
1000 #iommu-cells = <0>;
1004 display_subsystem: display-subsystem {
1005 compatible = "rockchip,display-subsystem";
1010 compatible = "rockchip,rk3228-dw-hdmi";
1012 reg-io-width = <4>;
1017 clock-names = "isfr", "iahb", "cec";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
1021 reset-names = "hdmi";
1023 phy-names = "hdmi_phy";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1033 remote-endpoint = <&vop_out_hdmi>;
1040 compatible = "rockchip,rk3328-tve";
1051 nvmem-cells = <&tve_dac>;
1052 nvmem-cell-names = "tve_dac_adj";
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1061 remote-endpoint = <&vop_out_tve>;
1068 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
1073 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1074 fifo-depth = <0x100>;
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
1081 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
1086 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1087 fifo-depth = <0x100>;
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
1094 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
1097 clock-frequency = <37500000>;
1098 clock-freq-min-max = <400000 37500000>;
1101 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1102 bus-width = <8>;
1103 default-sample-phase = <158>;
1104 num-slots = <1>;
1105 fifo-depth = <0x100>;
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1112 compatible = "rockchip,rk-nandc";
1117 clock-names = "clk_nandc", "hclk_nandc";
1122 compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
1127 clock-names = "otg";
1129 g-np-tx-fifo-size = <16>;
1130 g-rx-fifo-size = <280>;
1131 g-tx-fifo-size = <256 128 128 64 32 16>;
1132 g-use-dma;
1134 phy-names = "usb2-phy";
1139 compatible = "generic-ehci";
1143 clock-names = "usbhost", "utmi";
1145 phy-names = "usb";
1150 compatible = "generic-ohci";
1154 clock-names = "usbhost", "utmi";
1156 phy-names = "usb";
1161 compatible = "generic-ehci";
1165 clock-names = "usbhost", "utmi";
1167 phy-names = "usb";
1172 compatible = "generic-ohci";
1176 clock-names = "usbhost", "utmi";
1178 phy-names = "usb";
1183 compatible = "generic-ehci";
1188 phy-names = "usb";
1189 clock-names = "usbhost", "utmi";
1194 compatible = "generic-ohci";
1198 clock-names = "usbhost", "utmi";
1200 phy-names = "usb";
1205 compatible = "rockchip,rk3228-gmac";
1208 interrupt-names = "macirq";
1213 clock-names = "stmmaceth", "mac_clk_rx",
1218 reset-names = "stmmaceth", "mac-phy";
1238 gic: interrupt-controller@32010000 {
1239 compatible = "arm,gic-400";
1240 interrupt-controller;
1241 #interrupt-cells = <3>;
1242 #address-cells = <0>;
1252 compatible = "rockchip,rk3228-pinctrl";
1254 #address-cells = <1>;
1255 #size-cells = <1>;
1259 compatible = "rockchip,gpio-bank";
1264 gpio-controller;
1265 #gpio-cells = <2>;
1267 interrupt-controller;
1268 #interrupt-cells = <2>;
1272 compatible = "rockchip,gpio-bank";
1277 gpio-controller;
1278 #gpio-cells = <2>;
1280 interrupt-controller;
1281 #interrupt-cells = <2>;
1285 compatible = "rockchip,gpio-bank";
1290 gpio-controller;
1291 #gpio-cells = <2>;
1293 interrupt-controller;
1294 #interrupt-cells = <2>;
1298 compatible = "rockchip,gpio-bank";
1303 gpio-controller;
1304 #gpio-cells = <2>;
1306 interrupt-controller;
1307 #interrupt-cells = <2>;
1310 pcfg_pull_up: pcfg-pull-up {
1311 bias-pull-up;
1314 pcfg_pull_down: pcfg-pull-down {
1315 bias-pull-down;
1318 pcfg_pull_none: pcfg-pull-none {
1319 bias-disable;
1322 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1323 drive-strength = <12>;
1327 sdmmc_clk: sdmmc-clk {
1331 sdmmc_cmd: sdmmc-cmd {
1335 sdmmc_bus4: sdmmc-bus4 {
1344 sdio_clk: sdio-clk {
1348 sdio_cmd: sdio-cmd {
1352 sdio_bus4: sdio-bus4 {
1361 emmc_clk: emmc-clk {
1365 emmc_cmd: emmc-cmd {
1369 emmc_bus8: emmc-bus8 {
1382 rgmii_pins: rgmii-pins {
1400 rmii_pins: rmii-pins {
1413 phy_pins: phy-pins {
1420 hdmi_hpd: hdmi-hpd {
1424 hdmii2c_xfer: hdmii2c-xfer {
1429 hdmi_cec: hdmi-cec {
1435 i2c0_xfer: i2c0-xfer {
1442 i2c1_xfer: i2c1-xfer {
1449 i2c2_xfer: i2c2-xfer {
1456 i2c3_xfer: i2c3-xfer {
1463 tsp_d0: tsp-d0 {
1466 tsp_d1: tsp-d1 {
1469 tsp_d2: tsp-d2 {
1472 tsp_d3: tsp-d3 {
1475 tsp_d4: tsp-d4 {
1478 tsp_d5: tsp-d5 {
1481 tsp_d6: tsp-d6 {
1484 tsp_d7: tsp-d7 {
1487 tsp_sync: tsp-sync {
1490 tsp_clk: tsp-clk {
1493 tsp_fail: tsp-fail {
1496 tsp_valid: tsp-valid {
1501 spi-0 {
1502 spi0_clk: spi0-clk {
1505 spi0_cs0: spi0-cs0 {
1508 spi0_tx: spi0-tx {
1511 spi0_rx: spi0-rx {
1514 spi0_cs1: spi0-cs1 {
1519 spi-1 {
1520 spi1_clk: spi1-clk {
1523 spi1_cs0: spi1-cs0 {
1526 spi1_rx: spi1-rx {
1529 spi1_tx: spi1-tx {
1532 spi1_cs1: spi1-cs1 {
1538 i2s1_bus: i2s1-bus {
1552 pwm0_pin: pwm0-pin {
1556 pwm0_pin_pull_down: pwm0-pin-pull-down {
1560 pwm0_pin_pull_down: pwm0-pin-pull-down {
1566 pwm1_pin: pwm1-pin {
1570 pwm1_pin_pull_down: pwm1-pin-pull-down {
1574 pwm1_pin_pull_down: pwm1-pin-pull-down {
1580 pwm2_pin: pwm2-pin {
1584 pwm2_pin_pull_down: pwm2-pin-pull-down {
1588 pwm2_pin_pull_down: pwm2-pin-pull-down {
1594 pwm3_pin: pwm3-pin {
1598 pwm3_pin_pull_down: pwm3-pin-pull-down {
1602 pwm3_pin_pull_down: pwm3-pin-pull-down {
1608 spdif_tx: spdif-tx {
1614 otp_gpio: otp-gpio {
1618 otp_out: otp-out {
1624 uart0_xfer: uart0-xfer {
1629 uart0_cts: uart0-cts {
1633 uart0_rts: uart0-rts {
1639 uart1_xfer: uart1-xfer {
1644 uart1_cts: uart1-cts {
1648 uart1_rts: uart1-rts {
1653 uart1-1 {
1654 uart11_xfer: uart11-xfer {
1659 uart11_cts: uart11-cts {
1663 uart11_rts: uart11-rts {
1667 uart11_rts_gpio: uart11-rts-gpio {
1673 uart2_xfer: uart2-xfer {
1678 uart2_cts: uart2-cts {
1682 uart2_rts: uart2-rts {
1687 uart2-1 {
1688 uart21_xfer: uart21-xfer {
1696 compatible = "arm,psci-1.0";
1700 rockchip_suspend: rockchip-suspend {
1701 compatible = "rockchip,pm-rk322x";
1703 rockchip,virtual-poweroff = <0>;
1704 rockchip,sleep-mode-config = <