Lines Matching +full:rk3066 +full:- +full:smp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "rockchip,rk3066-smp";
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
35 operating-points-v2 = <&cpu0_opp_table>;
40 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
43 operating-points-v2 = <&cpu0_opp_table>;
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-312000000 {
52 opp-hz = /bits/ 64 <312000000>;
53 opp-microvolt = <1075000 1075000 1125000>;
54 clock-latency-ns = <40000>;
57 opp-504000000 {
58 opp-hz = /bits/ 64 <504000000>;
59 opp-microvolt = <1100000 1100000 1125000>;
60 clock-latency-ns = <40000>;
63 opp-816000000 {
64 opp-hz = /bits/ 64 <816000000>;
65 opp-microvolt = <1125000 1125000 1125000>;
66 clock-latency-ns = <40000>;
69 opp-1008000000 {
70 opp-hz = /bits/ 64 <1008000000>;
71 opp-microvolt = <1125000 1125000 1125000>;
72 clock-latency-ns = <40000>;
77 display-subsystem {
78 compatible = "rockchip,display-subsystem";
83 compatible = "mmio-sram";
85 #address-cells = <1>;
86 #size-cells = <1>;
89 smp-sram@0 {
90 compatible = "rockchip,rk3066-smp-sram";
109 reg-names = "Mali_L2",
131 interrupt-names = "Mali_GP_IRQ",
142 clock-names = "clk_mali";
144 operating-points-v2 = <&gpu_opp_table>;
148 compatible = "arm,mali-simple-power-model";
151 static-power = <300>;
152 dynamic-power = <396>;
153 ts = <32000 4700 (-80) 2>;
154 thermal-zone = "gpu-thermal";
158 gpu_opp_table: opp-table2 {
159 compatible = "operating-points-v2";
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 opp-microvolt = <1050000>;
165 opp-400000000 {
166 opp-hz = /bits/ 64 <400000000>;
167 opp-microvolt = <1275000>;
173 compatible = "rockchip,rk3066-vop";
179 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
180 power-domains = <&power RK3066_PD_VIO>;
184 reset-names = "axi", "ahb", "dclk";
188 #address-cells = <1>;
189 #size-cells = <0>;
193 remote-endpoint = <&hdmi_in_vop0>;
199 compatible = "rockchip,rk3066-vop";
205 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
206 power-domains = <&power RK3066_PD_VIO>;
210 reset-names = "axi", "ahb", "dclk";
214 #address-cells = <1>;
215 #size-cells = <0>;
219 remote-endpoint = <&hdmi_in_vop1>;
225 compatible = "rockchip,rk3066-hdmi";
229 clock-names = "hclk";
230 pinctrl-names = "default";
231 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
232 power-domains = <&power RK3066_PD_VIO>;
237 #address-cells = <1>;
238 #size-cells = <0>;
242 #address-cells = <1>;
243 #size-cells = <0>;
247 remote-endpoint = <&vop0_out_hdmi>;
252 remote-endpoint = <&vop1_out_hdmi>;
263 compatible = "rockchip,rk3066-i2s";
266 pinctrl-names = "default";
267 pinctrl-0 = <&i2s0_bus>;
269 dma-names = "tx", "rx";
270 clock-names = "i2s_hclk", "i2s_clk";
273 reset-names = "reset-m";
274 rockchip,playback-channels = <8>;
275 rockchip,capture-channels = <2>;
276 #sound-dai-cells = <0>;
281 compatible = "rockchip,rk3066-i2s";
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2s1_bus>;
287 dma-names = "tx", "rx";
288 clock-names = "i2s_hclk", "i2s_clk";
291 reset-names = "reset-m";
292 rockchip,playback-channels = <2>;
293 rockchip,capture-channels = <2>;
294 #sound-dai-cells = <0>;
299 compatible = "rockchip,rk3066-i2s";
302 pinctrl-names = "default";
303 pinctrl-0 = <&i2s2_bus>;
305 dma-names = "tx", "rx";
306 clock-names = "i2s_hclk", "i2s_clk";
309 reset-names = "reset-m";
310 rockchip,playback-channels = <2>;
311 rockchip,capture-channels = <2>;
312 #sound-dai-cells = <0>;
316 cru: clock-controller@20000000 {
317 compatible = "rockchip,rk3066a-cru";
321 #clock-cells = <1>;
322 #reset-cells = <1>;
324 assigned-clocks =
330 assigned-clock-rates =
339 compatible = "snps,dw-apb-timer-osc";
343 clock-names = "timer", "pclk";
347 compatible = "rockchip,rk3066a-efuse";
349 #address-cells = <1>;
350 #size-cells = <1>;
352 clock-names = "pclk_efuse";
360 compatible = "snps,dw-apb-timer-osc";
364 clock-names = "timer", "pclk";
368 compatible = "snps,dw-apb-timer-osc";
372 clock-names = "timer", "pclk";
376 compatible = "rockchip,rk3066-tsadc";
379 clock-names = "saradc", "apb_pclk";
381 #io-channel-cells = <1>;
383 reset-names = "saradc-apb";
388 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
390 #address-cells = <1>;
391 #size-cells = <0>;
394 usbphy0: usb-phy@17c {
395 #phy-cells = <0>;
398 clock-names = "phyclk";
399 #clock-cells = <0>;
402 usbphy1: usb-phy@188 {
403 #phy-cells = <0>;
406 clock-names = "phyclk";
407 #clock-cells = <0>;
412 compatible = "rockchip,rk3066a-pinctrl";
414 #address-cells = <1>;
415 #size-cells = <1>;
419 compatible = "rockchip,gpio-bank";
422 clock-names = "bus";
425 gpio-controller;
426 #gpio-cells = <2>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
433 compatible = "rockchip,gpio-bank";
436 clock-names = "bus";
439 gpio-controller;
440 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
447 compatible = "rockchip,gpio-bank";
450 clock-names = "bus";
453 gpio-controller;
454 #gpio-cells = <2>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
461 compatible = "rockchip,gpio-bank";
464 clock-names = "bus";
467 gpio-controller;
468 #gpio-cells = <2>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
475 compatible = "rockchip,gpio-bank";
478 clock-names = "bus";
481 gpio-controller;
482 #gpio-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
489 compatible = "rockchip,gpio-bank";
492 clock-names = "bus";
495 gpio-controller;
496 #gpio-cells = <2>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
503 bias-pull-pin-default;
507 bias-disable;
511 emac_xfer: emac-xfer {
522 emac_mdio: emac-mdio {
529 emmc_clk: emmc-clk {
533 emmc_cmd: emmc-cmd {
537 emmc_rst: emmc-rst {
545 * flash/emmc is the boot-device.
550 hdmi_hpd: hdmi-hpd {
554 hdmii2c_xfer: hdmii2c-xfer {
561 i2c0_xfer: i2c0-xfer {
568 i2c1_xfer: i2c1-xfer {
575 i2c2_xfer: i2c2-xfer {
582 i2c3_xfer: i2c3-xfer {
589 i2c4_xfer: i2c4-xfer {
596 pwm0_out: pwm0-out {
602 pwm1_out: pwm1-out {
608 pwm2_out: pwm2-out {
614 pwm3_out: pwm3-out {
620 spi0_clk: spi0-clk {
623 spi0_cs0: spi0-cs0 {
626 spi0_tx: spi0-tx {
629 spi0_rx: spi0-rx {
632 spi0_cs1: spi0-cs1 {
638 spi1_clk: spi1-clk {
641 spi1_cs0: spi1-cs0 {
644 spi1_rx: spi1-rx {
647 spi1_tx: spi1-tx {
650 spi1_cs1: spi1-cs1 {
656 uart0_xfer: uart0-xfer {
661 uart0_cts: uart0-cts {
665 uart0_rts: uart0-rts {
671 uart1_xfer: uart1-xfer {
676 uart1_cts: uart1-cts {
680 uart1_rts: uart1-rts {
686 uart2_xfer: uart2-xfer {
694 uart3_xfer: uart3-xfer {
699 uart3_cts: uart3-cts {
703 uart3_rts: uart3-rts {
709 sd0_clk: sd0-clk {
713 sd0_cmd: sd0-cmd {
717 sd0_cd: sd0-cd {
721 sd0_wp: sd0-wp {
725 sd0_bus1: sd0-bus-width1 {
729 sd0_bus4: sd0-bus-width4 {
738 sd1_clk: sd1-clk {
742 sd1_cmd: sd1-cmd {
746 sd1_cd: sd1-cd {
750 sd1_wp: sd1-wp {
754 sd1_bus1: sd1-bus-width1 {
758 sd1_bus4: sd1-bus-width4 {
767 i2s0_bus: i2s0-bus {
781 i2s1_bus: i2s1-bus {
792 i2s2_bus: i2s2-bus {
805 compatible = "rockchip,rk3066-mali", "arm,mali-400";
816 interrupt-names = "gp",
826 power-domains = <&power RK3066_PD_GPU>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&i2c0_xfer>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&i2c1_xfer>;
840 pinctrl-names = "default";
841 pinctrl-0 = <&i2c2_xfer>;
845 pinctrl-names = "default";
846 pinctrl-0 = <&i2c3_xfer>;
850 pinctrl-names = "default";
851 pinctrl-0 = <&i2c4_xfer>;
855 clock-frequency = <50000000>;
857 dma-names = "rx-tx";
858 max-frequency = <50000000>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
865 dma-names = "rx-tx";
866 pinctrl-names = "default";
867 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
872 dma-names = "rx-tx";
876 power: power-controller {
877 compatible = "rockchip,rk3066-power-controller";
878 #power-domain-cells = <1>;
879 #address-cells = <1>;
880 #size-cells = <0>;
882 power-domain@RK3066_PD_VIO {
909 power-domain@RK3066_PD_VIDEO {
918 power-domain@RK3066_PD_GPU {
927 pinctrl-names = "active";
928 pinctrl-0 = <&pwm0_out>;
932 pinctrl-names = "active";
933 pinctrl-0 = <&pwm1_out>;
937 pinctrl-names = "active";
938 pinctrl-0 = <&pwm2_out>;
942 pinctrl-names = "active";
943 pinctrl-0 = <&pwm3_out>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
957 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
959 dma-names = "tx", "rx";
960 pinctrl-names = "default";
961 pinctrl-0 = <&uart0_xfer>;
965 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
967 dma-names = "tx", "rx";
968 pinctrl-names = "default";
969 pinctrl-0 = <&uart1_xfer>;
973 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
975 dma-names = "tx", "rx";
976 pinctrl-names = "default";
977 pinctrl-0 = <&uart2_xfer>;
981 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
983 dma-names = "tx", "rx";
984 pinctrl-names = "default";
985 pinctrl-0 = <&uart3_xfer>;
989 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
993 compatible = "rockchip,rk3066-emac";