drivers/infineon/siutils_priv.h

111 	uint	coreid[SI_MAXCORES];	/**< id of each core */
141 	uint	dev_coreid;		/**< the core provides driver functions */
152 	uint varsz;
156 	uint	curidx;			/**< current core index */
157 	uint	numcores;		/**< # discovered cores */
166 	uint	chipnew;		/**< new chip number */
167 	uint second_bar0win;		/**< Backplane region */
168 	uint	num_br;		/**< # discovered bridges */
174 	uint	axi_num_wrappers;
186 #define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
241 extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
242 extern uint sb_coreid(si_t *sih);
243 extern uint sb_intflag(si_t *sih);
244 extern uint sb_flag(si_t *sih);
246 extern uint sb_corevendor(si_t *sih);
247 extern uint sb_corerev(si_t *sih);
248 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
249 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
251 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx);
260 extern uint32 sb_addrspace(si_t *sih, uint asidx);
261 extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
264 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
278 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
281 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
282                        void *sdh, char **vars, uint *varsz);
284 extern void ai_scan(si_t *sih, void *regs, uint32 erombase, uint devid);
286 extern uint ai_flag(si_t *sih);
287 extern uint ai_flag_alt(si_t *sih);
289 extern uint ai_coreidx(si_t *sih);
290 extern uint ai_corevendor(si_t *sih);
291 extern uint ai_corerev(si_t *sih);
292 extern uint ai_corerev_minor(si_t *sih);
293 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
295 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx);
296 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
297 extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx);
301 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
302 extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
310 extern uint32 ai_addrspace(si_t *sih, uint spidx, uint baidx);
311 extern uint32 ai_addrspacesize(si_t *sih, uint spidx, uint baidx);
312 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
313 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
316 void ai_force_clocks(si_t *sih, uint clock_state);
317 extern uint ai_num_slaveports(si_t *sih, uint coreidx);
324 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap);