infineon/include/siutils.h

68 	uint	socitype;		/**< SOCI_SB, SOCI_AI */
70 	uint	bustype;		/**< SI_BUS, PCI_BUS */
71 	uint	buscoretype;		/**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
72 	uint	buscorerev;		/**< buscore rev */
73 	uint	buscoreidx;		/**< buscore index */
79 	uint	boardtype;		/**< board type */
80 	uint    boardrev;               /* board rev */
81 	uint	boardvendor;		/**< board vendor */
82 	uint	boardflags;		/**< board flags */
83 	uint	boardflags2;		/**< board flags2 */
84 	uint	boardflags4;		/**< board flags4 */
85 	uint	chip;			/**< chip number */
86 	uint	chiprev;		/**< chip revision */
87 	uint	chippkg;		/**< chip package option */
90 	uint    socirev;		/**< SOC interconnect rev */
236 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
237                        void *sdh, char **vars, uint *varsz);
241 si_d11_switch_addrbase(si_t *sih, uint coreunit);
242 extern uint si_corelist(si_t *sih, uint coreid[]);
243 extern uint si_coreid(si_t *sih);
244 extern uint si_flag(si_t *sih);
245 extern uint si_flag_alt(si_t *sih);
246 extern uint si_intflag(si_t *sih);
247 extern uint si_coreidx(si_t *sih);
248 extern uint si_coreunit(si_t *sih);
249 extern uint si_corevendor(si_t *sih);
250 extern uint si_corerev(si_t *sih);
251 extern uint si_corerev_minor(si_t *sih);
254 extern int si_backplane_access(si_t *sih, uint addr, uint size,
255 	uint *val, bool read);
256 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
257 extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
258 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
259 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
261 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
262 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
269 extern uint si_numcoreunits(si_t *sih, uint coreid);
270 extern uint si_numd11coreunits(si_t *sih);
271 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
272 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
273 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
275 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
276 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
278 extern uint32 si_addrspace(si_t *sih, uint spidx, uint baidx);
279 extern uint32 si_addrspacesize(si_t *sih, uint spidx, uint baidx);
280 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
285 extern uint si_chip_hostif(si_t *sih);
289 extern void si_pci_setup(si_t *sih, uint coremask);
298 extern bool si_clkctl_cc(si_t *sih, uint mode);
299 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
314 extern void si_watchdog(si_t *sih, uint ticks);
329 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
367 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
368 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
377 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
447 extern void si_chippkg_set(si_t *sih, uint);
472 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
491 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
506 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
507 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
508 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
509 extern uint32 si_gci_input(si_t *sih, uint reg);
526 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
527 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
749 void si_config_4364_d11_oob(si_t *sih, uint coreid);
752 extern uint si_num_slaveports(si_t *sih, uint coreid);
753 extern uint32 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx,
754 	uint core_id, uint coreunit);
755 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint spidx,
756 	uint baidx, uint coreunit);
757 uint si_introff(si_t *sih);
758 void si_intrrestore(si_t *sih, uint intr_val);
810 uint32 si_enum_base(uint devid);
811 uint32 si_pcie_enum_base(uint devid);
819 void si_clrirq_idx(si_t *sih, uint core_idx);