Lines Matching full:transmit
30 * basic DMA register set is per channel(transmit or receive)
72 /* transmit channel control */
73 #define XC_XE ((uint32)1 << 0) /**< transmit enable */
74 #define XC_SE ((uint32)1 << 1) /**< transmit suspend request */
127 /* transmit descriptor table pointer */
130 /* transmit channel status */
132 #define XS_XS_MASK 0xf000 /**< transmit state */
139 #define XS_XE_MASK 0xf0000 /**< transmit errors */
192 #define FA_SEL_XDD 0x00000 /**< transmit dma data */
193 #define FA_SEL_XDP 0x10000 /**< transmit dma pointers */
196 #define FA_SEL_XFD 0x80000 /**< transmit fifo data */
197 #define FA_SEL_XFP 0x90000 /**< transmit fifo pointers */
288 /* transmit channel control */
289 #define D64_XC_XE 0x00000001 /**< transmit enable */
290 #define D64_XC_SE 0x00000002 /**< transmit suspend request */
309 /* transmit descriptor table pointer */
312 /* transmit channel status */
314 #define D64_XS0_XS_MASK 0xf0000000 /**< transmit state */
323 #define D64_XS1_XE_MASK 0xf0000000 /**< transmit errors */
427 #define D64_FA_SEL_XDD 0x00000 /**< transmit dma data */
428 #define D64_FA_SEL_XDP 0x10000 /**< transmit dma pointers */
431 #define D64_FA_SEL_XFD 0x80000 /**< transmit fifo data */
432 #define D64_FA_SEL_XFP 0x90000 /**< transmit fifo pointers */
441 /**< bzero operation for receive channels or a compare-to-zero operation for transmit engines */