Lines Matching +full:0 +full:xf0000
73 #define XC_XE ((uint32)1 << 0) /**< transmit enable */
77 #define XC_MR_MASK 0x000001C0 /**< Multiple outstanding reads */
82 #define XC_BL_MASK 0x001C0000 /**< BurstLen bits */
84 #define XC_PC_MASK 0x00E00000 /**< Prefetch control */
86 #define XC_PT_MASK 0x03000000 /**< Prefetch threshold */
90 #define DMA_MR_1 0
100 #define DMA_BL_16 0
107 #define DMA_BL_INVALID 0xFF
110 #define DMA_PC_0 0
118 #define DMA_PT_1 0
124 #define DMA_CS_OFF 0
128 #define XP_LD_MASK 0xfff /**< last valid descriptor */
131 #define XS_CD_MASK 0x0fff /**< current descriptor pointer */
132 #define XS_XS_MASK 0xf000 /**< transmit state */
134 #define XS_XS_DISABLED 0x0000 /**< disabled */
135 #define XS_XS_ACTIVE 0x1000 /**< active */
136 #define XS_XS_IDLE 0x2000 /**< idle wait */
137 #define XS_XS_STOPPED 0x3000 /**< stopped */
138 #define XS_XS_SUSP 0x4000 /**< suspend pending */
139 #define XS_XE_MASK 0xf0000 /**< transmit errors */
141 #define XS_XE_NOERR 0x00000 /**< no error */
142 #define XS_XE_DPE 0x10000 /**< descriptor protocol error */
143 #define XS_XE_DFU 0x20000 /**< data fifo underrun */
144 #define XS_XE_BEBR 0x30000 /**< bus error on buffer read */
145 #define XS_XE_BEDA 0x40000 /**< bus error on descriptor access */
146 #define XS_AD_MASK 0xfff00000 /**< active descriptor */
150 #define RC_RE ((uint32)1 << 0) /**< receive enable */
151 #define RC_RO_MASK 0xfe /**< receive frame offset */
159 #define RC_BL_MASK 0x001C0000 /**< BurstLen bits */
161 #define RC_PC_MASK 0x00E00000 /**< Prefetch control */
163 #define RC_PT_MASK 0x03000000 /**< Prefetch threshold */
165 #define RC_WAITCMP_MASK 0x00001000
168 #define RP_LD_MASK 0xfff /**< last valid descriptor */
171 #define RS_CD_MASK 0x0fff /**< current descriptor pointer */
172 #define RS_RS_MASK 0xf000 /**< receive state */
174 #define RS_RS_DISABLED 0x0000 /**< disabled */
175 #define RS_RS_ACTIVE 0x1000 /**< active */
176 #define RS_RS_IDLE 0x2000 /**< idle wait */
177 #define RS_RS_STOPPED 0x3000 /**< reserved */
178 #define RS_RE_MASK 0xf0000 /**< receive errors */
180 #define RS_RE_NOERR 0x00000 /**< no error */
181 #define RS_RE_DPE 0x10000 /**< descriptor protocol error */
182 #define RS_RE_DFO 0x20000 /**< data fifo overflow */
183 #define RS_RE_BEBW 0x30000 /**< bus error on buffer write */
184 #define RS_RE_BEDA 0x40000 /**< bus error on descriptor access */
185 #define RS_AD_MASK 0xfff00000 /**< active descriptor */
189 #define FA_OFF_MASK 0xffff /**< offset */
190 #define FA_SEL_MASK 0xf0000 /**< select */
192 #define FA_SEL_XDD 0x00000 /**< transmit dma data */
193 #define FA_SEL_XDP 0x10000 /**< transmit dma pointers */
194 #define FA_SEL_RDD 0x40000 /**< receive dma data */
195 #define FA_SEL_RDP 0x50000 /**< receive dma pointers */
196 #define FA_SEL_XFD 0x80000 /**< transmit fifo data */
197 #define FA_SEL_XFP 0x90000 /**< transmit fifo pointers */
198 #define FA_SEL_RFD 0xc0000 /**< receive fifo data */
199 #define FA_SEL_RFP 0xd0000 /**< receive fifo pointers */
200 #define FA_SEL_RSD 0xe0000 /**< receive frame status data */
201 #define FA_SEL_RSP 0xf0000 /**< receive frame status pointers */
204 #define CTRL_BC_MASK 0x00001fff /**< buffer byte count, real data len must <= 4KB */
214 #define CTRL_CORE_MASK 0x0ff00000
247 uint32 addrlow; /**< memory address of the date buffer, bits 31:0 */
289 #define D64_XC_XE 0x00000001 /**< transmit enable */
290 #define D64_XC_SE 0x00000002 /**< transmit suspend request */
291 #define D64_XC_LE 0x00000004 /**< loopback enable */
292 #define D64_XC_FL 0x00000010 /**< flush request */
293 #define D64_XC_MR_MASK 0x000001C0 /**< Multiple outstanding reads */
296 #define D64_XC_CS_MASK 0x00000200 /**< channel switch enable */
297 #define D64_XC_PD 0x00000800 /**< parity check disable */
298 #define D64_XC_AE 0x00030000 /**< address extension bits */
300 #define D64_XC_BL_MASK 0x001C0000 /**< BurstLen bits */
302 #define D64_XC_PC_MASK 0x00E00000 /**< Prefetch control */
304 #define D64_XC_PT_MASK 0x03000000 /**< Prefetch threshold */
306 #define D64_XC_CO_MASK 0x04000000 /**< coherent transactions for descriptors */
310 #define D64_XP_LD_MASK 0x00001fff /**< last valid descriptor */
314 #define D64_XS0_XS_MASK 0xf0000000 /**< transmit state */
316 #define D64_XS0_XS_DISABLED 0x00000000 /**< disabled */
317 #define D64_XS0_XS_ACTIVE 0x10000000 /**< active */
318 #define D64_XS0_XS_IDLE 0x20000000 /**< idle wait */
319 #define D64_XS0_XS_STOPPED 0x30000000 /**< stopped */
320 #define D64_XS0_XS_SUSP 0x40000000 /**< suspend pending */
323 #define D64_XS1_XE_MASK 0xf0000000 /**< transmit errors */
325 #define D64_XS1_XE_NOERR 0x00000000 /**< no error */
326 #define D64_XS1_XE_DPE 0x10000000 /**< descriptor protocol error */
327 #define D64_XS1_XE_DFU 0x20000000 /**< data fifo underrun */
328 #define D64_XS1_XE_DTE 0x30000000 /**< data transfer error */
329 #define D64_XS1_XE_DESRE 0x40000000 /**< descriptor read error */
330 #define D64_XS1_XE_COREE 0x50000000 /**< core error */
333 #define D64_RC_RE 0x00000001 /**< receive enable */
334 #define D64_RC_RO_MASK 0x000000fe /**< receive frame offset */
336 #define D64_RC_FM 0x00000100 /**< direct fifo receive (pio) mode */
337 #define D64_RC_SH 0x00000200 /**< separate rx header descriptor enable */
339 #define D64_RC_OC 0x00000400 /**< overflow continue */
340 #define D64_RC_PD 0x00000800 /**< parity check disable */
341 #define D64_RC_WAITCMP_MASK 0x00001000
343 #define D64_RC_SA 0x00002000 /**< select active */
344 #define D64_RC_GE 0x00004000 /**< Glom enable */
345 #define D64_RC_AE 0x00030000 /**< address extension bits */
347 #define D64_RC_BL_MASK 0x001C0000 /**< BurstLen bits */
349 #define D64_RC_PC_MASK 0x00E00000 /**< Prefetch control */
351 #define D64_RC_PT_MASK 0x03000000 /**< Prefetch threshold */
353 #define D64_RC_CO_MASK 0x04000000 /**< coherent transactions for descriptors */
355 #define D64_RC_ROEXT_MASK 0x08000000 /**< receive frame offset extension bit */
358 #define D64_RC_MOW_MASK ((0x3u) << D64_RC_MOW_SHIFT)
364 #define D64_RC_MOW_1 (0u) /**< 1 outstanding write */
370 #define DMA_CTRL_PEN (1u << 0u) /**< partity enable */
391 #define DMA_CTRL_COREUNIT_MASK (0x3u << 17u) /* Core unit mask */
401 #define D64_RP_LD_MASK 0x00001fff /**< last valid descriptor */
405 #define D64_RS0_RS_MASK 0xf0000000 /**< receive state */
407 #define D64_RS0_RS_DISABLED 0x00000000 /**< disabled */
408 #define D64_RS0_RS_ACTIVE 0x10000000 /**< active */
409 #define D64_RS0_RS_IDLE 0x20000000 /**< idle wait */
410 #define D64_RS0_RS_STOPPED 0x30000000 /**< stopped */
411 #define D64_RS0_RS_SUSP 0x40000000 /**< suspend pending */
414 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
416 #define D64_RS1_RE_NOERR 0x00000000 /**< no error */
417 #define D64_RS1_RE_DPO 0x10000000 /**< descriptor protocol error */
418 #define D64_RS1_RE_DFU 0x20000000 /**< data fifo overflow */
419 #define D64_RS1_RE_DTE 0x30000000 /**< data transfer error */
420 #define D64_RS1_RE_DESRE 0x40000000 /**< descriptor read error */
421 #define D64_RS1_RE_COREE 0x50000000 /**< core error */
424 #define D64_FA_OFF_MASK 0xffff /**< offset */
425 #define D64_FA_SEL_MASK 0xf0000 /**< select */
427 #define D64_FA_SEL_XDD 0x00000 /**< transmit dma data */
428 #define D64_FA_SEL_XDP 0x10000 /**< transmit dma pointers */
429 #define D64_FA_SEL_RDD 0x40000 /**< receive dma data */
430 #define D64_FA_SEL_RDP 0x50000 /**< receive dma pointers */
431 #define D64_FA_SEL_XFD 0x80000 /**< transmit fifo data */
432 #define D64_FA_SEL_XFP 0x90000 /**< transmit fifo pointers */
433 #define D64_FA_SEL_RFD 0xc0000 /**< receive fifo data */
434 #define D64_FA_SEL_RFP 0xd0000 /**< receive fifo pointers */
435 #define D64_FA_SEL_RSD 0xe0000 /**< receive frame status data */
436 #define D64_FA_SEL_RSP 0xf0000 /**< receive frame status pointers */
439 #define D64_CTRL_COREFLAGS 0x0ff00000 /**< core specific flags */
452 #define D64_CTRL1_SOFPTR 0x0000FFFFu
453 #define D64_CTRL1_NUMD_MASK 0x00F00000u
457 #define D64_CTRL2_MAX_LEN 0x0000fff7 /* Max transfer length (buffer byte count) <= 65527 */
458 #define D64_CTRL2_BC_MASK 0x0000ffff /**< mask for buffer byte count */
459 #define D64_CTRL2_AE 0x00030000 /**< address extension bits */
461 #define D64_CTRL2_PARITY 0x00040000 /* parity bit */
464 #define D64_CTRL_CORE_MASK 0x0ff00000
466 #define D64_RX_FRM_STS_LEN 0x0000ffff /**< frame length mask */
467 #define D64_RX_FRM_STS_OVFL 0x00800000 /**< RxOverFlow */
468 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /**< no. of descriptors used - 1, d11corerev >= 22 */
470 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /**< core-dependent data type */