Merge branch 'next' of ../next

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

The number of CPUs are getting detected dynamically by checking the
processor SVR value. Also removed CONFIG_NUM_CPUS references from all
the platforms

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

The number of CPUs are getting detected dynamically by checking the
processor SVR value. Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Removed BEDBUG support from FSL 85xx boards

For some reason the MPC8544 enabled BEDBUG if PCI was enabled and that
got copied int the MPC8536, MPC8572 and P2020 DS boards. The BEDBUG
support

85xx: Removed BEDBUG support from FSL 85xx boards

For some reason the MPC8544 enabled BEDBUG if PCI was enabled and that
got copied int the MPC8536, MPC8572 and P2020 DS boards. The BEDBUG
support has never been made to work completely on e500/85xx so we
just disable it to save space and match the other FSL 85xx boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of /home/wd/git/u-boot/custodians

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

85xx: Report which "bank" of NOR flash we are booting from on FSL boards

The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot

85xx: Report which "bank" of NOR flash we are booting from on FSL boards

The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks. This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".

The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Bump up the BOOTMAP to 16M on FSL 85xx boards

We have always mapped at least 16M in the kernel and we have seen cases
with new kernel features that a kernel image needs more than 8M of
memory.

85xx: Bump up the BOOTMAP to 16M on FSL 85xx boards

We have always mapped at least 16M in the kernel and we have seen cases
with new kernel features that a kernel image needs more than 8M of
memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of /home/wd/git/u-boot/master

remove _IO_BASE and KSEG1ADDR from board configuration files

The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet
driver, but the code that used that macro was removed over a year
ago,

remove _IO_BASE and KSEG1ADDR from board configuration files

The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet
driver, but the code that used that macro was removed over a year
ago, so board configuration files no longer need to define it.

The _IO_BASE macro is also automatically defined to 0 if it isn't
already set, so there's no need to define that macro either in the
board configuration files.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

8xxx: Fix PCI bus address setup for 36-bit configs

We want the outbound PCI memory map to end at the 4G boundary so we
can maximize the amount of space available for inbound mappings if
we have larg

8xxx: Fix PCI bus address setup for 36-bit configs

We want the outbound PCI memory map to end at the 4G boundary so we
can maximize the amount of space available for inbound mappings if
we have large amounts of memory.

This matches the device tree setup in the kernel for the 36-bit physical
configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'next' of ../master

i2c: Remove deprecated individual i2c commands

The following individual I2C commands have been removed: imd, imm, inm,
imw, icrc32, iprobe, iloop, isdram.

The functionality of the individual comman

i2c: Remove deprecated individual i2c commands

The following individual I2C commands have been removed: imd, imm, inm,
imw, icrc32, iprobe, iloop, isdram.

The functionality of the individual commands is still available via
the 'i2c' command.

This change only has an impact on those boards which did not have
CONFIG_I2C_CMD_TREE defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

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85xx: Fix address map for 36-bit config of MPC8572DS

When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map. Additionally, the change to the address
ma

85xx: Fix address map for 36-bit config of MPC8572DS

When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map. Additionally, the change to the address
map exposes a small issue in our dummy read on the ULI bus. We need
to use the new mapping functions to handle that read properly in the
36-bit config.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Fix how we map DDR memory

Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size

85xx: Fix how we map DDR memory

Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge git://git.denx.de/u-boot into u-boot

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

85xx: Add a 36-bit physical configuration for MPC8572DS

We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary
to allow for larger memory sizes.

Signed-off-by: Kumar Gala <galak@kerne

85xx: Add a 36-bit physical configuration for MPC8572DS

We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary
to allow for larger memory sizes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Handle eLBC difference w/36-bit physical

The eLBC only handles 32-bit physical address in systems with 36-bit
physical. The previos generation of LBC handled 34-bit physical
address in 36-bit

85xx: Handle eLBC difference w/36-bit physical

The eLBC only handles 32-bit physical address in systems with 36-bit
physical. The previos generation of LBC handled 34-bit physical
address in 36-bit systems. Added a new CONFIG option to convey
the difference between the LBC and eLBC.

Also added defines for XAM bits used in LBC for the extended 34-bit
support.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Use BR_ADDR macro for NAND chipselects

Use the new BR_ADDR macro to properly setup the address field of the
localbus chipselects used by NAND.

This allows us to deal with 36-bit phys on these

85xx: Use BR_ADDR macro for NAND chipselects

Use the new BR_ADDR macro to properly setup the address field of the
localbus chipselects used by NAND.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards

Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address. In most situations these are
map

85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards

Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

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85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards

Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapp

85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards

Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

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85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards

Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak

85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards

Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards

Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: K

85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards

Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

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85xx: separate FLASH BASE virtual from physical address

Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.

Th

85xx: separate FLASH BASE virtual from physical address

Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

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