1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8572ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8572 1 35 #define CONFIG_MPC8572DS 1 36 #define CONFIG_MP 1 /* support multiple processors */ 37 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 38 39 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 40 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 41 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 42 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 43 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 /* 54 * When initializing flash, if we cannot find the manufacturer ID, 55 * assume this is the AMD flash associated with the CDS board. 56 * This allows booting from a promjet. 57 */ 58 #define CONFIG_ASSUME_AMD_FLASH 59 60 #ifndef __ASSEMBLY__ 61 extern unsigned long get_board_sys_clk(unsigned long dummy); 62 extern unsigned long get_board_ddr_clk(unsigned long dummy); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 65 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 66 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 67 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 68 from ICS307 instead of switches */ 69 70 /* 71 * These can be toggled for performance analysis, otherwise use default. 72 */ 73 #define CONFIG_L2_CACHE /* toggle L2 cache */ 74 #define CONFIG_BTB /* toggle branch predition */ 75 76 #define CONFIG_ENABLE_36BIT_PHYS 1 77 78 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 79 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 80 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 81 82 /* 83 * Base addresses -- Note these are effective addresses where the 84 * actual resources get mapped (not physical addresses) 85 */ 86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 87 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 89 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 90 91 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 92 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 93 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 94 95 /* DDR Setup */ 96 #define CONFIG_SYS_DDR_TLB_START 9 97 #define CONFIG_FSL_DDR2 98 #undef CONFIG_FSL_DDR_INTERACTIVE 99 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 100 #define CONFIG_DDR_SPD 101 #undef CONFIG_DDR_DLL 102 103 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 104 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 105 106 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 108 109 #define CONFIG_NUM_DDR_CONTROLLERS 2 110 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 111 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 112 113 /* I2C addresses of SPD EEPROMs */ 114 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 115 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 116 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 117 118 /* These are used when DDR doesn't use SPD. */ 119 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 120 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 121 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 122 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 123 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 124 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 125 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 126 #define CONFIG_SYS_DDR_MODE_1 0x00440462 127 #define CONFIG_SYS_DDR_MODE_2 0x00000000 128 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 129 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 130 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 131 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 132 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 133 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 134 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 135 136 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 137 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 138 #define CONFIG_SYS_DDR_SBE 0x00010000 139 140 /* 141 * Make sure required options are set 142 */ 143 #ifndef CONFIG_SPD_EEPROM 144 #error ("CONFIG_SPD_EEPROM is required") 145 #endif 146 147 #undef CONFIG_CLOCKS_IN_MHZ 148 149 /* 150 * Memory map 151 * 152 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 153 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 154 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 155 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 156 * 157 * Localbus cacheable (TBD) 158 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 159 * 160 * Localbus non-cacheable 161 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 162 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 163 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 164 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 165 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 166 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 167 */ 168 169 /* 170 * Local Bus Definitions 171 */ 172 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174 175 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 176 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 177 178 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180 181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 182 #define CONFIG_SYS_FLASH_QUIET_TEST 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 184 185 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 191 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 197 198 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 199 200 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 201 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 202 #define PIXIS_BASE_PHYS PIXIS_BASE 203 204 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 205 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 206 207 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 208 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 209 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 210 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 211 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 212 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 213 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 214 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 215 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 216 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 217 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 218 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 219 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 220 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 221 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 222 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 223 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 224 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 225 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 226 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 227 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 228 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 229 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 230 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 231 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 232 #define PIXIS_LED 0x25 /* LED Register */ 233 234 /* old pixis referenced names */ 235 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 236 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 237 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 238 #define PIXIS_VSPEED2_TSEC1SER 0x8 239 #define PIXIS_VSPEED2_TSEC2SER 0x4 240 #define PIXIS_VSPEED2_TSEC3SER 0x2 241 #define PIXIS_VSPEED2_TSEC4SER 0x1 242 #define PIXIS_VCFGEN1_TSEC1SER 0x20 243 #define PIXIS_VCFGEN1_TSEC2SER 0x20 244 #define PIXIS_VCFGEN1_TSEC3SER 0x20 245 #define PIXIS_VCFGEN1_TSEC4SER 0x20 246 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 247 | PIXIS_VSPEED2_TSEC2SER \ 248 | PIXIS_VSPEED2_TSEC3SER \ 249 | PIXIS_VSPEED2_TSEC4SER) 250 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 251 | PIXIS_VCFGEN1_TSEC2SER \ 252 | PIXIS_VCFGEN1_TSEC3SER \ 253 | PIXIS_VCFGEN1_TSEC4SER) 254 255 #define CONFIG_SYS_INIT_RAM_LOCK 1 256 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 257 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 258 259 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 260 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 261 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 262 263 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 264 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 265 266 #define CONFIG_SYS_NAND_BASE 0xffa00000 267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 268 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 269 CONFIG_SYS_NAND_BASE + 0x40000, \ 270 CONFIG_SYS_NAND_BASE + 0x80000,\ 271 CONFIG_SYS_NAND_BASE + 0xC0000} 272 #define CONFIG_SYS_MAX_NAND_DEVICE 4 273 #define CONFIG_MTD_NAND_VERIFY_WRITE 274 #define CONFIG_CMD_NAND 1 275 #define CONFIG_NAND_FSL_ELBC 1 276 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 277 278 /* NAND flash config */ 279 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 280 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 281 | BR_PS_8 /* Port Size = 8 bit */ \ 282 | BR_MS_FCM /* MSEL = FCM */ \ 283 | BR_V) /* valid */ 284 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 285 | OR_FCM_PGS /* Large Page*/ \ 286 | OR_FCM_CSCT \ 287 | OR_FCM_CST \ 288 | OR_FCM_CHT \ 289 | OR_FCM_SCY_1 \ 290 | OR_FCM_TRLX \ 291 | OR_FCM_EHTR) 292 293 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 294 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 295 296 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 297 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 298 | BR_PS_8 /* Port Size = 8 bit */ \ 299 | BR_MS_FCM /* MSEL = FCM */ \ 300 | BR_V) /* valid */ 301 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 302 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 303 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 304 | BR_PS_8 /* Port Size = 8 bit */ \ 305 | BR_MS_FCM /* MSEL = FCM */ \ 306 | BR_V) /* valid */ 307 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 308 309 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 310 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 311 | BR_PS_8 /* Port Size = 8 bit */ \ 312 | BR_MS_FCM /* MSEL = FCM */ \ 313 | BR_V) /* valid */ 314 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 315 316 317 /* Serial Port - controlled on board with jumper J8 318 * open - index 2 319 * shorted - index 1 320 */ 321 #define CONFIG_CONS_INDEX 1 322 #undef CONFIG_SERIAL_SOFTWARE_FIFO 323 #define CONFIG_SYS_NS16550 324 #define CONFIG_SYS_NS16550_SERIAL 325 #define CONFIG_SYS_NS16550_REG_SIZE 1 326 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 333 334 /* Use the HUSH parser */ 335 #define CONFIG_SYS_HUSH_PARSER 336 #ifdef CONFIG_SYS_HUSH_PARSER 337 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 338 #endif 339 340 /* 341 * Pass open firmware flat tree 342 */ 343 #define CONFIG_OF_LIBFDT 1 344 #define CONFIG_OF_BOARD_SETUP 1 345 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 346 347 #define CONFIG_SYS_64BIT_VSPRINTF 1 348 #define CONFIG_SYS_64BIT_STRTOUL 1 349 350 /* new uImage format support */ 351 #define CONFIG_FIT 1 352 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 353 354 /* I2C */ 355 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 356 #define CONFIG_HARD_I2C /* I2C with hardware support */ 357 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 358 #define CONFIG_I2C_MULTI_BUS 359 #define CONFIG_I2C_CMD_TREE 360 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 361 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 362 #define CONFIG_SYS_I2C_SLAVE 0x7F 363 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 364 #define CONFIG_SYS_I2C_OFFSET 0x3000 365 #define CONFIG_SYS_I2C2_OFFSET 0x3100 366 367 /* 368 * I2C2 EEPROM 369 */ 370 #define CONFIG_ID_EEPROM 371 #ifdef CONFIG_ID_EEPROM 372 #define CONFIG_SYS_I2C_EEPROM_NXID 373 #endif 374 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 375 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 376 #define CONFIG_SYS_EEPROM_BUS_NUM 1 377 378 /* 379 * General PCI 380 * Memory space is mapped 1-1, but I/O space must start from 0. 381 */ 382 383 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 384 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 385 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 386 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 387 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 388 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 389 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 390 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 391 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 392 393 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 394 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 395 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 396 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 397 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 398 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 399 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 400 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 401 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 402 403 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 404 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 405 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 406 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 407 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 408 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 409 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 410 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 411 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 412 413 #if defined(CONFIG_PCI) 414 415 /*PCIE video card used*/ 416 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 417 418 /* video */ 419 #define CONFIG_VIDEO 420 421 #if defined(CONFIG_VIDEO) 422 #define CONFIG_BIOSEMU 423 #define CONFIG_CFB_CONSOLE 424 #define CONFIG_VIDEO_SW_CURSOR 425 #define CONFIG_VGA_AS_SINGLE_DEVICE 426 #define CONFIG_ATI_RADEON_FB 427 #define CONFIG_VIDEO_LOGO 428 /*#define CONFIG_CONSOLE_CURSOR*/ 429 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 430 #endif 431 432 #define CONFIG_NET_MULTI 433 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 434 435 #undef CONFIG_EEPRO100 436 #undef CONFIG_TULIP 437 #undef CONFIG_RTL8139 438 439 #ifdef CONFIG_RTL8139 440 /* This macro is used by RTL8139 but not defined in PPC architecture */ 441 #define KSEG1ADDR(x) (x) 442 #define _IO_BASE 0x00000000 443 #endif 444 445 #ifndef CONFIG_PCI_PNP 446 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 447 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 448 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 449 #endif 450 451 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 452 #define CONFIG_DOS_PARTITION 453 #define CONFIG_SCSI_AHCI 454 455 #ifdef CONFIG_SCSI_AHCI 456 #define CONFIG_SATA_ULI5288 457 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 458 #define CONFIG_SYS_SCSI_MAX_LUN 1 459 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 460 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 461 #endif /* SCSI */ 462 463 #endif /* CONFIG_PCI */ 464 465 466 #if defined(CONFIG_TSEC_ENET) 467 468 #ifndef CONFIG_NET_MULTI 469 #define CONFIG_NET_MULTI 1 470 #endif 471 472 #define CONFIG_MII 1 /* MII PHY management */ 473 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 474 #define CONFIG_TSEC1 1 475 #define CONFIG_TSEC1_NAME "eTSEC1" 476 #define CONFIG_TSEC2 1 477 #define CONFIG_TSEC2_NAME "eTSEC2" 478 #define CONFIG_TSEC3 1 479 #define CONFIG_TSEC3_NAME "eTSEC3" 480 #define CONFIG_TSEC4 1 481 #define CONFIG_TSEC4_NAME "eTSEC4" 482 483 #define CONFIG_PIXIS_SGMII_CMD 484 #define CONFIG_FSL_SGMII_RISER 1 485 #define SGMII_RISER_PHY_OFFSET 0x1c 486 487 #ifdef CONFIG_FSL_SGMII_RISER 488 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 489 #endif 490 491 #define TSEC1_PHY_ADDR 0 492 #define TSEC2_PHY_ADDR 1 493 #define TSEC3_PHY_ADDR 2 494 #define TSEC4_PHY_ADDR 3 495 496 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 497 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 498 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 499 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 500 501 #define TSEC1_PHYIDX 0 502 #define TSEC2_PHYIDX 0 503 #define TSEC3_PHYIDX 0 504 #define TSEC4_PHYIDX 0 505 506 #define CONFIG_ETHPRIME "eTSEC1" 507 508 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 509 #endif /* CONFIG_TSEC_ENET */ 510 511 /* 512 * Environment 513 */ 514 #define CONFIG_ENV_IS_IN_FLASH 1 515 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 516 #define CONFIG_ENV_ADDR 0xfff80000 517 #else 518 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 519 #endif 520 #define CONFIG_ENV_SIZE 0x2000 521 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 522 523 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 524 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 525 526 /* 527 * Command line configuration. 528 */ 529 #include <config_cmd_default.h> 530 531 #define CONFIG_CMD_IRQ 532 #define CONFIG_CMD_PING 533 #define CONFIG_CMD_I2C 534 #define CONFIG_CMD_MII 535 #define CONFIG_CMD_ELF 536 #define CONFIG_CMD_IRQ 537 #define CONFIG_CMD_SETEXPR 538 539 #if defined(CONFIG_PCI) 540 #define CONFIG_CMD_PCI 541 #define CONFIG_CMD_BEDBUG 542 #define CONFIG_CMD_NET 543 #define CONFIG_CMD_SCSI 544 #define CONFIG_CMD_EXT2 545 #endif 546 547 #undef CONFIG_WATCHDOG /* watchdog disabled */ 548 549 /* 550 * Miscellaneous configurable options 551 */ 552 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 553 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 554 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 555 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 556 #if defined(CONFIG_CMD_KGDB) 557 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 558 #else 559 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 560 #endif 561 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 562 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 563 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 564 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 565 566 /* 567 * For booting Linux, the board info and command line data 568 * have to be in the first 8 MB of memory, since this is 569 * the maximum mapped by the Linux kernel during initialization. 570 */ 571 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 572 573 /* 574 * Internal Definitions 575 * 576 * Boot Flags 577 */ 578 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 579 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 580 581 #if defined(CONFIG_CMD_KGDB) 582 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 583 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 584 #endif 585 586 /* 587 * Environment Configuration 588 */ 589 590 /* The mac addresses for all ethernet interface */ 591 #if defined(CONFIG_TSEC_ENET) 592 #define CONFIG_HAS_ETH0 593 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 594 #define CONFIG_HAS_ETH1 595 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 596 #define CONFIG_HAS_ETH2 597 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 598 #define CONFIG_HAS_ETH3 599 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 600 #endif 601 602 #define CONFIG_IPADDR 192.168.1.254 603 604 #define CONFIG_HOSTNAME unknown 605 #define CONFIG_ROOTPATH /opt/nfsroot 606 #define CONFIG_BOOTFILE uImage 607 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 608 609 #define CONFIG_SERVERIP 192.168.1.1 610 #define CONFIG_GATEWAYIP 192.168.1.1 611 #define CONFIG_NETMASK 255.255.255.0 612 613 /* default location for tftp and bootm */ 614 #define CONFIG_LOADADDR 1000000 615 616 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 617 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 618 619 #define CONFIG_BAUDRATE 115200 620 621 #define CONFIG_EXTRA_ENV_SETTINGS \ 622 "memctl_intlv_ctl=2\0" \ 623 "netdev=eth0\0" \ 624 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 625 "tftpflash=tftpboot $loadaddr $uboot; " \ 626 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 627 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 628 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 629 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 630 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 631 "consoledev=ttyS0\0" \ 632 "ramdiskaddr=2000000\0" \ 633 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 634 "fdtaddr=c00000\0" \ 635 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 636 "bdev=sda3\0" 637 638 #define CONFIG_HDBOOT \ 639 "setenv bootargs root=/dev/$bdev rw " \ 640 "console=$consoledev,$baudrate $othbootargs;" \ 641 "tftp $loadaddr $bootfile;" \ 642 "tftp $fdtaddr $fdtfile;" \ 643 "bootm $loadaddr - $fdtaddr" 644 645 #define CONFIG_NFSBOOTCOMMAND \ 646 "setenv bootargs root=/dev/nfs rw " \ 647 "nfsroot=$serverip:$rootpath " \ 648 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 649 "console=$consoledev,$baudrate $othbootargs;" \ 650 "tftp $loadaddr $bootfile;" \ 651 "tftp $fdtaddr $fdtfile;" \ 652 "bootm $loadaddr - $fdtaddr" 653 654 #define CONFIG_RAMBOOTCOMMAND \ 655 "setenv bootargs root=/dev/ram rw " \ 656 "console=$consoledev,$baudrate $othbootargs;" \ 657 "tftp $ramdiskaddr $ramdiskfile;" \ 658 "tftp $loadaddr $bootfile;" \ 659 "tftp $fdtaddr $fdtfile;" \ 660 "bootm $loadaddr $ramdiskaddr $fdtaddr" 661 662 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 663 664 #endif /* __CONFIG_H */ 665