| 2c66af11 | 01-Mar-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: fix the function vop2_power_domain_on()
1.Remove the pd_data of plane "Esmart0", which is not
controlled by SYS_CTRL_POWER_CTRL[7].
2.Add the flag of is_enabled to avoid function
drm/rockchip: vop2: fix the function vop2_power_domain_on()
1.Remove the pd_data of plane "Esmart0", which is not
controlled by SYS_CTRL_POWER_CTRL[7].
2.Add the flag of is_enabled to avoid function being
called repeatedly.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I4a1367f72aedd79ecfa516c31d6f6b195d2ae3ee
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| 0b728e80 | 23-Feb-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: disabled aclk of video port when unused
To reduce power consumption.
Depend on the kernel commit:
Iebe8d071380ed998579942aeab7662a6ffda3cb0
"drm/rockchip: vop2: Disable aclk of
drm/rockchip: vop2: disabled aclk of video port when unused
To reduce power consumption.
Depend on the kernel commit:
Iebe8d071380ed998579942aeab7662a6ffda3cb0
"drm/rockchip: vop2: Disable aclk of video port when it unused"
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I4437906c1967633648fbcc67cfe3dae652986d2d
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| a33b790f | 28-Feb-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: add support for axi setting
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ibb592ae01ce805f8ffa650437823a3b481d72324 |
| 3e20b04e | 28-Feb-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: modify the function of pd switch
Open the pd of primary plane when vp enabled.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ie8dbecd4c7efede0421b703c05495abb
drm/rockchip: vop2: modify the function of pd switch
Open the pd of primary plane when vp enabled.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ie8dbecd4c7efede0421b703c05495abb52d752d1
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| d3e70420 | 08-Mar-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Set link power state
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I69e08c0d010dfc94e375c9c107abe9e14d7f4b70 |
| 1a00cf6e | 08-Mar-2022 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Use link train delay helper
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iba67c1d1dfc7ad62cf95cd95b212fe1abdfa69c0 |
| 9f076ecc | 02-Mar-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
drm/rockchip: vop2: change dclk calculate method for mipi
When the video port request pixelclk under 600Mhz, it
should set the dclk_rate : pixelclk_rate as 1 : 1. So
It can calculate the same divide
drm/rockchip: vop2: change dclk calculate method for mipi
When the video port request pixelclk under 600Mhz, it
should set the dclk_rate : pixelclk_rate as 1 : 1. So
It can calculate the same divider ratio for dclk core
rate and dclk out rate when different output interface
(MIPI, DP and HDMI) connect to th same video port.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I6037e12d8b6be904a74add0649b1a1f62c4fe3d4
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| d2e91fdc | 07-Jan-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: fix internal power domain on/off status check when memory bisr enabled
When query vop internal power domain on/off status from
PMU BISR_STS3, 1 is for power up, 0 is for power do
drm/rockchip: vop2: fix internal power domain on/off status check when memory bisr enabled
When query vop internal power domain on/off status from
PMU BISR_STS3, 1 is for power up, 0 is for power down,
this is different from the pd status in vop.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I4da6b50e49932d46f6abdaf6899bf6411019bae4
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| 6b2bd269 | 24-Feb-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: vop2: fix dp dclk calculation issue
When DP interface output YUV420 format image, it nedd calculate
the dclk according to dclk_out_rate. It can avoid the dclk_out_rate
divide value overfl
video/drm: vop2: fix dp dclk calculation issue
When DP interface output YUV420 format image, it nedd calculate
the dclk according to dclk_out_rate. It can avoid the dclk_out_rate
divide value overflow.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ifa279113ae43fc3ad581262c1bf3007858c0ef30
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| fb43630c | 22-Jan-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: Add dw dp driver
This add a DisplayPort driver for Synopsys DW DP Controller.
Porting from Linux develop-5.10 commit 9548fbb10c90 ("drm/rockchip:
Add support for Synopsys DesignWare Core
video/drm: Add dw dp driver
This add a DisplayPort driver for Synopsys DW DP Controller.
Porting from Linux develop-5.10 commit 9548fbb10c90 ("drm/rockchip:
Add support for Synopsys DesignWare Cores DPTX")
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9c310e6195c17616366e42af6bb49229ce408a98
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| ebdfc6a4 | 11-Feb-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: add drm dp helper functions
Sync from kernel-5.10:
According to Linux Kernel drm dp helper functions, Add some
common defines and functions for DP interface.
Signed-off-by: Zhang Yubing
video/drm: add drm dp helper functions
Sync from kernel-5.10:
According to Linux Kernel drm dp helper functions, Add some
common defines and functions for DP interface.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I385b797590e4f825f5692fa081ba51a979bd4f43
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| a12a16bb | 24-Feb-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Set hdmi output interface when force output
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I1cae7cbbf728ab38328123322f2d2a54d3727a57 |
| 0d7a8537 | 23-Feb-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support rk3588 hdmi force-output mode
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I828f94b005ed6a5ca6eec1ac96c8ac55da396c6c |
| 108c5f8b | 12-Feb-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: vop2: config dp1 output enable bit
When select dp1 output interface, we need set dp1 enable bit,
not hdmi.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ie5dd222a7
video/drm: vop2: config dp1 output enable bit
When select dp1 output interface, we need set dp1 enable bit,
not hdmi.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ie5dd222a7c48590e3637809402c31f4c0c46daff
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| e24e9033 | 24-Jan-2022 |
Sandy Huang <hjc@rock-chips.com> |
video/drm: vop2: set lineflag trigger time
lineflag0: maybe used for PSR panel, we sent at the last active line;
lineflag1: for current dmc policy, lineflag1 no need to advanced 3 ms;
Signed-off-by
video/drm: vop2: set lineflag trigger time
lineflag0: maybe used for PSR panel, we sent at the last active line;
lineflag1: for current dmc policy, lineflag1 no need to advanced 3 ms;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I24d1ca68d433adf31009a07e6f3278ca92c565c6
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| 55b28e7d | 14-Feb-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: phy-rockchip-samsung-hdptx-hdmi: Register phy pll as child device
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ifd27057bca766aaab5b02280d6ffdc2828cef691 |
| 545a0218 | 14-Feb-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: vop2: Get hdmi phy pll by name
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibbb0789e8f430677eb58488a7458ff36aaebc820 |
| 3e59c137 | 08-Feb-2022 |
Sandy Huang <hjc@rock-chips.com> |
video/drm: vop2: add support uv swap for some bt1120 busformat
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia485413f7dffc114f3cec227fadd47fbe1fc4fd5 |
| b890760e | 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
drm/rockchip: vop2: Support RK3588 hdmi logo
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I7e6373435bb3f19a61cd23c39ccca75430faa53e |
| 28671eda | 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support dw-hdmi-qp
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I63477c492a3f570f06c958f2aec3bd5c7cbdca25 |
| fea6cfaa | 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: Add samsung combphy hdmi driver
HDMI phy-pll may be used as dclk source.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id61ac5a9a04a8ec7068329c02567c33f3a2fe7c5 |
| 67be2ffc | 14-Jan-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: fix the core_dclk_div_sel setting
When the display interface is BT656. the register of
core_dclk_div_sel should always be set 1. Not only 'i'
modes like 480i and 576i, but also '
drm/rockchip: vop2: fix the core_dclk_div_sel setting
When the display interface is BT656. the register of
core_dclk_div_sel should always be set 1. Not only 'i'
modes like 480i and 576i, but also 'p' modes like 720p,
both need this setting.
As for BT1120 and other interfaces, this bit should be
1 when display mode belongs to 'i', and 0 when display
mode belongs to 'p'.
Only RK3568 has the core_dclk_div_sel control bit, which
has been removed on RK3588.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ifdd3aef5541f4170eb5085da01a0820f1d713971
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| 65747de7 | 17-Jan-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop2: set rg swap for rk3588 hdmi/dp yuv444 output
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I6c25872d179349d904d6a7e0ce210e8a16269cf7 |
| b3e1cbde | 22-Jan-2022 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: display: modify the log of getting base2_disp_info
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I3fda2a2921403f1413cece758d5025e4570fdb25 |
| 629c727b | 15-Dec-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: rockchip_phy: update for px30s
- px30s: add support 2.5Gsps lane rate
- disable pin_txclkesc inverting
- reset digital logic before select phy lvds mode
- reset digital logic before selec
video/drm: rockchip_phy: update for px30s
- px30s: add support 2.5Gsps lane rate
- disable pin_txclkesc inverting
- reset digital logic before select phy lvds mode
- reset digital logic before select TTL mode
Change-Id: I6d5c1e94fe995d386e45484805c753dbdf70128e
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
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