1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/io.h> 18 #include <dm/lists.h> 19 #include <clk.h> 20 #include <clk-uclass.h> 21 #include <reset.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /** 26 * If the temperature over a period of time High, 27 * the resulting TSHUT gave CRU module,let it reset the entire chip, 28 * or via GPIO give PMIC. 29 */ 30 enum tshut_mode { 31 TSHUT_MODE_CRU = 0, 32 TSHUT_MODE_GPIO, 33 }; 34 35 /** 36 * The system Temperature Sensors tshut(tshut) polarity 37 * the bit 8 is tshut polarity. 38 * 0: low active, 1: high active 39 */ 40 enum tshut_polarity { 41 TSHUT_LOW_ACTIVE = 0, 42 TSHUT_HIGH_ACTIVE, 43 }; 44 45 /** 46 * The conversion table has the adc value and temperature. 47 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 48 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 49 */ 50 enum adc_sort_mode { 51 ADC_DECREMENT = 0, 52 ADC_INCREMENT, 53 }; 54 55 #define SOC_MAX_SENSORS 7 56 57 #define TSADCV2_USER_CON 0x00 58 #define TSADCV2_AUTO_CON 0x04 59 #define TSADCV2_INT_EN 0x08 60 #define TSADCV2_INT_PD 0x0c 61 #define TSADCV3_AUTO_SRC_CON 0x0c 62 #define TSADCV3_HT_INT_EN 0x14 63 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18 64 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c 65 #define TSADCV3_INT_PD 0x24 66 #define TSADCV3_HSHUT_PD 0x28 67 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 68 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 69 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 70 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) 71 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) 72 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) 73 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 74 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 75 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c 76 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 77 #define TSADCV2_AUTO_PERIOD 0x68 78 #define TSADCV2_AUTO_PERIOD_HT 0x6c 79 #define TSADCV3_AUTO_PERIOD 0x154 80 #define TSADCV3_AUTO_PERIOD_HT 0x158 81 82 #define TSADCV2_AUTO_EN BIT(0) 83 #define TSADCV2_AUTO_EN_MASK BIT(16) 84 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 85 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) 86 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + (chn)) 87 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 88 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) 89 90 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 91 92 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 93 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) 94 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 95 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 96 97 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 98 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 99 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff 100 101 #define TSADCV2_DATA_MASK 0xfff 102 #define TSADCV3_DATA_MASK 0x3ff 103 #define TSADCV4_DATA_MASK 0x1ff 104 105 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 106 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 107 #define TSADCV2_AUTO_PERIOD_TIME 250 108 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 109 #define TSADCV3_AUTO_PERIOD_TIME 1875 110 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 111 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ 112 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ 113 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ 114 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ 115 116 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 117 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ 118 119 #define GRF_SARADC_TESTBIT 0x0e644 120 #define GRF_TSADC_TESTBIT_L 0x0e648 121 #define GRF_TSADC_TESTBIT_H 0x0e64c 122 123 #define PX30_GRF_SOC_CON2 0x0408 124 125 #define RK3568_GRF_TSADC_CON 0x0600 126 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) 127 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) 128 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) 129 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) 130 131 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 132 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 133 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 134 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 135 136 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 137 138 #define MIN_TEMP (-40000) 139 #define LOWEST_TEMP (-273000) 140 #define MAX_TEMP (125000) 141 #define MAX_ENV_TEMP (85000) 142 143 #define BASE (1024) 144 #define BASE_SHIFT (10) 145 #define START_DEBOUNCE_COUNT (100) 146 #define HIGHER_DEBOUNCE_TEMP (30000) 147 #define LOWER_DEBOUNCE_TEMP (15000) 148 149 /** 150 * struct tsadc_table - hold information about code and temp mapping 151 * @code: raw code from tsadc ip 152 * @temp: the mapping temperature 153 */ 154 155 struct tsadc_table { 156 unsigned long code; 157 int temp; 158 }; 159 160 struct chip_tsadc_table { 161 const struct tsadc_table *id; 162 unsigned int length; 163 u32 data_mask; 164 /* Tsadc is linear, using linear parameters */ 165 int knum; 166 int bnum; 167 enum adc_sort_mode mode; 168 }; 169 170 enum sensor_id { 171 SENSOR_CPU = 0, 172 SENSOR_GPU, 173 }; 174 175 struct rockchip_tsadc_chip { 176 /* The sensor id of chip correspond to the ADC channel */ 177 int chn_id[SOC_MAX_SENSORS]; 178 int chn_num; 179 fdt_addr_t base; 180 fdt_addr_t grf; 181 182 /* The hardware-controlled tshut property */ 183 int tshut_temp; 184 enum tshut_mode tshut_mode; 185 enum tshut_polarity tshut_polarity; 186 187 void (*tsadc_control)(struct udevice *dev, bool enable); 188 void (*tsadc_init)(struct udevice *dev); 189 int (*tsadc_get_temp)(struct udevice *dev, int chn, 190 int *temp); 191 void (*irq_ack)(struct udevice *dev); 192 void (*set_alarm_temp)(struct udevice *dev, 193 int chn, int temp); 194 void (*set_tshut_temp)(struct udevice *dev, 195 int chn, int temp); 196 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 197 struct chip_tsadc_table table; 198 }; 199 200 struct rockchip_thermal_priv { 201 void *base; 202 void *grf; 203 enum tshut_mode tshut_mode; 204 enum tshut_polarity tshut_polarity; 205 const struct rockchip_tsadc_chip *data; 206 }; 207 208 static const struct tsadc_table rk1808_code_table[] = { 209 {0, -40000}, 210 {3455, -40000}, 211 {3463, -35000}, 212 {3471, -30000}, 213 {3479, -25000}, 214 {3487, -20000}, 215 {3495, -15000}, 216 {3503, -10000}, 217 {3511, -5000}, 218 {3519, 0}, 219 {3527, 5000}, 220 {3535, 10000}, 221 {3543, 15000}, 222 {3551, 20000}, 223 {3559, 25000}, 224 {3567, 30000}, 225 {3576, 35000}, 226 {3584, 40000}, 227 {3592, 45000}, 228 {3600, 50000}, 229 {3609, 55000}, 230 {3617, 60000}, 231 {3625, 65000}, 232 {3633, 70000}, 233 {3642, 75000}, 234 {3650, 80000}, 235 {3659, 85000}, 236 {3667, 90000}, 237 {3675, 95000}, 238 {3684, 100000}, 239 {3692, 105000}, 240 {3701, 110000}, 241 {3709, 115000}, 242 {3718, 120000}, 243 {3726, 125000}, 244 {TSADCV2_DATA_MASK, 125000}, 245 }; 246 247 static const struct tsadc_table rk3228_code_table[] = { 248 {0, -40000}, 249 {588, -40000}, 250 {593, -35000}, 251 {598, -30000}, 252 {603, -25000}, 253 {608, -20000}, 254 {613, -15000}, 255 {618, -10000}, 256 {623, -5000}, 257 {629, 0}, 258 {634, 5000}, 259 {639, 10000}, 260 {644, 15000}, 261 {649, 20000}, 262 {654, 25000}, 263 {660, 30000}, 264 {665, 35000}, 265 {670, 40000}, 266 {675, 45000}, 267 {681, 50000}, 268 {686, 55000}, 269 {691, 60000}, 270 {696, 65000}, 271 {702, 70000}, 272 {707, 75000}, 273 {712, 80000}, 274 {717, 85000}, 275 {723, 90000}, 276 {728, 95000}, 277 {733, 100000}, 278 {738, 105000}, 279 {744, 110000}, 280 {749, 115000}, 281 {754, 120000}, 282 {760, 125000}, 283 {TSADCV2_DATA_MASK, 125000}, 284 }; 285 286 static const struct tsadc_table rk3288_code_table[] = { 287 {TSADCV2_DATA_MASK, -40000}, 288 {3800, -40000}, 289 {3792, -35000}, 290 {3783, -30000}, 291 {3774, -25000}, 292 {3765, -20000}, 293 {3756, -15000}, 294 {3747, -10000}, 295 {3737, -5000}, 296 {3728, 0}, 297 {3718, 5000}, 298 {3708, 10000}, 299 {3698, 15000}, 300 {3688, 20000}, 301 {3678, 25000}, 302 {3667, 30000}, 303 {3656, 35000}, 304 {3645, 40000}, 305 {3634, 45000}, 306 {3623, 50000}, 307 {3611, 55000}, 308 {3600, 60000}, 309 {3588, 65000}, 310 {3575, 70000}, 311 {3563, 75000}, 312 {3550, 80000}, 313 {3537, 85000}, 314 {3524, 90000}, 315 {3510, 95000}, 316 {3496, 100000}, 317 {3482, 105000}, 318 {3467, 110000}, 319 {3452, 115000}, 320 {3437, 120000}, 321 {3421, 125000}, 322 }; 323 324 static const struct tsadc_table rk3328_code_table[] = { 325 {0, -40000}, 326 {296, -40000}, 327 {304, -35000}, 328 {313, -30000}, 329 {331, -20000}, 330 {340, -15000}, 331 {349, -10000}, 332 {359, -5000}, 333 {368, 0}, 334 {378, 5000}, 335 {388, 10000}, 336 {398, 15000}, 337 {408, 20000}, 338 {418, 25000}, 339 {429, 30000}, 340 {440, 35000}, 341 {451, 40000}, 342 {462, 45000}, 343 {473, 50000}, 344 {485, 55000}, 345 {496, 60000}, 346 {508, 65000}, 347 {521, 70000}, 348 {533, 75000}, 349 {546, 80000}, 350 {559, 85000}, 351 {572, 90000}, 352 {586, 95000}, 353 {600, 100000}, 354 {614, 105000}, 355 {629, 110000}, 356 {644, 115000}, 357 {659, 120000}, 358 {675, 125000}, 359 {TSADCV2_DATA_MASK, 125000}, 360 }; 361 362 static const struct tsadc_table rk3368_code_table[] = { 363 {0, -40000}, 364 {106, -40000}, 365 {108, -35000}, 366 {110, -30000}, 367 {112, -25000}, 368 {114, -20000}, 369 {116, -15000}, 370 {118, -10000}, 371 {120, -5000}, 372 {122, 0}, 373 {124, 5000}, 374 {126, 10000}, 375 {128, 15000}, 376 {130, 20000}, 377 {132, 25000}, 378 {134, 30000}, 379 {136, 35000}, 380 {138, 40000}, 381 {140, 45000}, 382 {142, 50000}, 383 {144, 55000}, 384 {146, 60000}, 385 {148, 65000}, 386 {150, 70000}, 387 {152, 75000}, 388 {154, 80000}, 389 {156, 85000}, 390 {158, 90000}, 391 {160, 95000}, 392 {162, 100000}, 393 {163, 105000}, 394 {165, 110000}, 395 {167, 115000}, 396 {169, 120000}, 397 {171, 125000}, 398 {TSADCV3_DATA_MASK, 125000}, 399 }; 400 401 static const struct tsadc_table rk3399_code_table[] = { 402 {0, -40000}, 403 {402, -40000}, 404 {410, -35000}, 405 {419, -30000}, 406 {427, -25000}, 407 {436, -20000}, 408 {444, -15000}, 409 {453, -10000}, 410 {461, -5000}, 411 {470, 0}, 412 {478, 5000}, 413 {487, 10000}, 414 {496, 15000}, 415 {504, 20000}, 416 {513, 25000}, 417 {521, 30000}, 418 {530, 35000}, 419 {538, 40000}, 420 {547, 45000}, 421 {555, 50000}, 422 {564, 55000}, 423 {573, 60000}, 424 {581, 65000}, 425 {590, 70000}, 426 {599, 75000}, 427 {607, 80000}, 428 {616, 85000}, 429 {624, 90000}, 430 {633, 95000}, 431 {642, 100000}, 432 {650, 105000}, 433 {659, 110000}, 434 {668, 115000}, 435 {677, 120000}, 436 {685, 125000}, 437 {TSADCV3_DATA_MASK, 125000}, 438 }; 439 440 static const struct tsadc_table rk3568_code_table[] = { 441 {0, -40000}, 442 {1584, -40000}, 443 {1620, -35000}, 444 {1652, -30000}, 445 {1688, -25000}, 446 {1720, -20000}, 447 {1756, -15000}, 448 {1788, -10000}, 449 {1824, -5000}, 450 {1856, 0}, 451 {1892, 5000}, 452 {1924, 10000}, 453 {1956, 15000}, 454 {1992, 20000}, 455 {2024, 25000}, 456 {2060, 30000}, 457 {2092, 35000}, 458 {2128, 40000}, 459 {2160, 45000}, 460 {2196, 50000}, 461 {2228, 55000}, 462 {2264, 60000}, 463 {2300, 65000}, 464 {2332, 70000}, 465 {2368, 75000}, 466 {2400, 80000}, 467 {2436, 85000}, 468 {2468, 90000}, 469 {2500, 95000}, 470 {2536, 100000}, 471 {2572, 105000}, 472 {2604, 110000}, 473 {2636, 115000}, 474 {2672, 120000}, 475 {2704, 125000}, 476 {TSADCV2_DATA_MASK, 125000}, 477 }; 478 479 static const struct tsadc_table rk3588_code_table[] = { 480 {0, -40000}, 481 {215, -40000}, 482 {285, 25000}, 483 {350, 85000}, 484 {395, 125000}, 485 {TSADCV4_DATA_MASK, 125000}, 486 }; 487 488 /* 489 * Struct used for matching a device 490 */ 491 struct of_device_id { 492 char compatible[32]; 493 const void *data; 494 }; 495 496 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 497 int *temp) 498 { 499 unsigned int low = 1; 500 unsigned int high = table->length - 1; 501 unsigned int mid = (low + high) / 2; 502 unsigned int num; 503 unsigned long denom; 504 505 if (table->knum) { 506 *temp = (((int)code - table->bnum) * 10000 / table->knum) * 100; 507 if (*temp < MIN_TEMP || *temp > MAX_TEMP) 508 return -EAGAIN; 509 return 0; 510 } 511 512 switch (table->mode) { 513 case ADC_DECREMENT: 514 code &= table->data_mask; 515 if (code < table->id[high].code) 516 return -EAGAIN; /* Incorrect reading */ 517 518 while (low <= high) { 519 if (code >= table->id[mid].code && 520 code < table->id[mid - 1].code) 521 break; 522 else if (code < table->id[mid].code) 523 low = mid + 1; 524 else 525 high = mid - 1; 526 527 mid = (low + high) / 2; 528 } 529 break; 530 case ADC_INCREMENT: 531 code &= table->data_mask; 532 if (code < table->id[low].code) 533 return -EAGAIN; /* Incorrect reading */ 534 535 while (low <= high) { 536 if (code <= table->id[mid].code && 537 code > table->id[mid - 1].code) 538 break; 539 else if (code > table->id[mid].code) 540 low = mid + 1; 541 else 542 high = mid - 1; 543 544 mid = (low + high) / 2; 545 } 546 break; 547 default: 548 printf("%s: Invalid the conversion table mode=%d\n", 549 __func__, table->mode); 550 return -EINVAL; 551 } 552 553 /* 554 * The 5C granularity provided by the table is too much. Let's 555 * assume that the relationship between sensor readings and 556 * temperature between 2 table entries is linear and interpolate 557 * to produce less granular result. 558 */ 559 num = table->id[mid].temp - table->id[mid - 1].temp; 560 num *= abs(table->id[mid - 1].code - code); 561 denom = abs(table->id[mid - 1].code - table->id[mid].code); 562 *temp = table->id[mid - 1].temp + (num / denom); 563 564 return 0; 565 } 566 567 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 568 int temp) 569 { 570 int high, low, mid; 571 unsigned long num; 572 unsigned int denom; 573 u32 error = table.data_mask; 574 575 if (table.knum) 576 return (((temp / 1000) * table.knum) / 1000 + table.bnum); 577 578 low = 0; 579 high = table.length - 1; 580 mid = (high + low) / 2; 581 582 /* Return mask code data when the temp is over table range */ 583 if (temp < table.id[low].temp || temp > table.id[high].temp) 584 goto exit; 585 586 while (low <= high) { 587 if (temp == table.id[mid].temp) 588 return table.id[mid].code; 589 else if (temp < table.id[mid].temp) 590 high = mid - 1; 591 else 592 low = mid + 1; 593 mid = (low + high) / 2; 594 } 595 596 num = abs(table.id[mid + 1].code - table.id[mid].code); 597 num *= temp - table.id[mid].temp; 598 denom = table.id[mid + 1].temp - table.id[mid].temp; 599 600 switch (table.mode) { 601 case ADC_DECREMENT: 602 return table.id[mid].code - (num / denom); 603 case ADC_INCREMENT: 604 return table.id[mid].code + (num / denom); 605 default: 606 pr_err("%s: unknown table mode: %d\n", __func__, table.mode); 607 return error; 608 } 609 610 exit: 611 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 612 __func__, error, temp); 613 614 return error; 615 } 616 617 static void tsadc_irq_ack_v2(struct udevice *dev) 618 { 619 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 620 u32 val; 621 622 val = readl(priv->base + TSADCV2_INT_PD); 623 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 624 } 625 626 static void tsadc_irq_ack_v3(struct udevice *dev) 627 { 628 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 629 u32 val; 630 631 val = readl(priv->base + TSADCV2_INT_PD); 632 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 633 } 634 635 static void tsadc_irq_ack_v4(struct udevice *dev) 636 { 637 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 638 u32 val; 639 640 val = readl(priv->base + TSADCV3_INT_PD); 641 writel(val & TSADCV4_INT_PD_CLEAR_MASK, priv->base + TSADCV3_INT_PD); 642 val = readl(priv->base + TSADCV3_HSHUT_PD); 643 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV3_HSHUT_PD); 644 } 645 646 static void tsadc_control_v2(struct udevice *dev, bool enable) 647 { 648 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 649 u32 val; 650 651 val = readl(priv->base + TSADCV2_AUTO_CON); 652 if (enable) 653 val |= TSADCV2_AUTO_EN; 654 else 655 val &= ~TSADCV2_AUTO_EN; 656 657 writel(val, priv->base + TSADCV2_AUTO_CON); 658 } 659 660 static void tsadc_control_v3(struct udevice *dev, bool enable) 661 { 662 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 663 u32 val; 664 665 val = readl(priv->base + TSADCV2_AUTO_CON); 666 if (enable) 667 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 668 else 669 val &= ~TSADCV2_AUTO_EN; 670 671 writel(val, priv->base + TSADCV2_AUTO_CON); 672 } 673 674 static void tsadc_control_v4(struct udevice *dev, bool enable) 675 { 676 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 677 u32 val; 678 679 if (enable) 680 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; 681 else 682 val = TSADCV2_AUTO_EN_MASK; 683 684 writel(val, priv->base + TSADCV2_AUTO_CON); 685 } 686 687 static void tsadc_init_v2(struct udevice *dev) 688 { 689 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 690 691 writel(TSADCV2_AUTO_PERIOD_TIME, 692 priv->base + TSADCV2_AUTO_PERIOD); 693 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 694 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 695 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 696 priv->base + TSADCV2_AUTO_PERIOD_HT); 697 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 698 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 699 700 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 701 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 702 priv->base + TSADCV2_AUTO_CON); 703 else 704 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 705 priv->base + TSADCV2_AUTO_CON); 706 } 707 708 static void tsadc_init_v3(struct udevice *dev) 709 { 710 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 711 712 if (!IS_ERR(priv->grf)) { 713 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 714 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 715 716 udelay(100);/* The spec note says at least 15 us */ 717 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 718 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 719 udelay(200);/* The spec note says at least 90 us */ 720 } 721 tsadc_init_v2(dev); 722 } 723 724 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 725 { 726 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 727 728 /* Set interleave value to workround ic time sync issue */ 729 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 730 TSADCV2_USER_CON); 731 tsadc_init_v2(dev); 732 } 733 734 static void tsadc_init_v4(struct udevice *dev) 735 { 736 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 737 738 tsadc_init_v2(dev); 739 if (!IS_ERR(priv->grf)) 740 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 741 } 742 743 static void tsadc_init_v7(struct udevice *dev) 744 { 745 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 746 747 writel(TSADCV5_USER_INTER_PD_SOC, 748 priv->base + TSADCV2_USER_CON); 749 writel(TSADCV5_AUTO_PERIOD_TIME, 750 priv->base + TSADCV2_AUTO_PERIOD); 751 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 752 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 753 writel(TSADCV5_AUTO_PERIOD_HT_TIME, 754 priv->base + TSADCV2_AUTO_PERIOD_HT); 755 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 756 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 757 758 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 759 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 760 priv->base + TSADCV2_AUTO_CON); 761 else 762 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 763 priv->base + TSADCV2_AUTO_CON); 764 765 if (!IS_ERR(priv->grf)) { 766 writel(RK3568_GRF_TSADC_TSEN, 767 priv->grf + RK3568_GRF_TSADC_CON); 768 udelay(15); 769 writel(RK3568_GRF_TSADC_ANA_REG0, 770 priv->grf + RK3568_GRF_TSADC_CON); 771 writel(RK3568_GRF_TSADC_ANA_REG1, 772 priv->grf + RK3568_GRF_TSADC_CON); 773 writel(RK3568_GRF_TSADC_ANA_REG2, 774 priv->grf + RK3568_GRF_TSADC_CON); 775 udelay(200); 776 } 777 } 778 779 static void tsadc_init_v8(struct udevice *dev) 780 { 781 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 782 783 writel(TSADCV6_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD); 784 writel(TSADCV6_AUTO_PERIOD_HT_TIME, 785 priv->base + TSADCV3_AUTO_PERIOD_HT); 786 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 787 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 788 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 789 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 790 791 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 792 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 793 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 794 priv->base + TSADCV2_AUTO_CON); 795 else 796 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 797 priv->base + TSADCV2_AUTO_CON); 798 } 799 800 static int tsadc_get_temp_v2(struct udevice *dev, 801 int chn, int *temp) 802 { 803 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 804 struct chip_tsadc_table table = priv->data->table; 805 u32 val; 806 807 val = readl(priv->base + TSADCV2_DATA(chn)); 808 809 return tsadc_code_to_temp(&table, val, temp); 810 } 811 812 static int predict_temp(int temp) 813 { 814 /* 815 * The deviation of prediction. the temperature will not change rapidly, 816 * so this cov_q is small 817 */ 818 int cov_q = 18; 819 /* 820 * The deviation of tsadc's reading, deviation of tsadc is very big when 821 * abnormal temperature is get 822 */ 823 int cov_r = 542; 824 825 int gain; 826 int temp_mid; 827 int temp_now; 828 int prob_mid; 829 int prob_now; 830 static int temp_last = LOWEST_TEMP; 831 static int prob_last = 160; 832 static int bounding_cnt; 833 834 /* 835 * init temp_last with a more suitable value, which mostly equals to 836 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 837 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 838 * value and temp_last is adjusted to MAX_ENV_TEMP. 839 */ 840 if (temp_last == LOWEST_TEMP) 841 temp_last = min(temp, MAX_ENV_TEMP); 842 843 /* 844 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 845 * tsadc is stable, i.e. after that, the temperature may be not stable 846 * and may have abnormal reading, so we set a bounding temperature. If 847 * the reading from tsadc is too big, we set the delta temperature of 848 * DEBOUNCE_TEMP/3 comparing to the last temperature. 849 */ 850 851 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 852 bounding_cnt = START_DEBOUNCE_COUNT; 853 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 854 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 855 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 856 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 857 } 858 859 temp_mid = temp_last; 860 861 /* calculate the probability of this time's prediction */ 862 prob_mid = prob_last + cov_q; 863 864 /* calculate the Kalman Gain */ 865 gain = (prob_mid * BASE) / (prob_mid + cov_r); 866 867 /* calculate the prediction of temperature */ 868 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 869 870 /* 871 * Base on this time's Kalman Gain, ajust our probability of prediction 872 * for next time calculation 873 */ 874 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 875 876 prob_last = prob_now; 877 temp_last = temp_now; 878 879 return temp_last; 880 } 881 882 static int tsadc_get_temp_v3(struct udevice *dev, 883 int chn, int *temp) 884 { 885 int ret; 886 887 ret = tsadc_get_temp_v2(dev, chn, temp); 888 if (!ret) 889 *temp = predict_temp(*temp); 890 891 return ret; 892 } 893 894 static int tsadc_get_temp_v4(struct udevice *dev, int chn, int *temp) 895 { 896 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 897 struct chip_tsadc_table table = priv->data->table; 898 u32 val; 899 900 val = readl(priv->base + TSADCV3_DATA(chn)); 901 902 return tsadc_code_to_temp(&table, val, temp); 903 } 904 905 static void tsadc_alarm_temp_v2(struct udevice *dev, 906 int chn, int temp) 907 { 908 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 909 struct chip_tsadc_table table = priv->data->table; 910 u32 alarm_value, int_en; 911 912 alarm_value = tsadc_temp_to_code_v2(table, temp); 913 if (alarm_value == table.data_mask) 914 return; 915 916 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 917 918 int_en = readl(priv->base + TSADCV2_INT_EN); 919 int_en |= TSADCV2_INT_SRC_EN(chn); 920 writel(int_en, priv->base + TSADCV2_INT_EN); 921 } 922 923 static void tsadc_alarm_temp_v3(struct udevice *dev, int chn, int temp) 924 { 925 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 926 struct chip_tsadc_table table = priv->data->table; 927 u32 alarm_value; 928 929 alarm_value = tsadc_temp_to_code_v2(table, temp); 930 if (alarm_value == table.data_mask) 931 return; 932 933 writel(alarm_value, priv->base + TSADCV3_COMP_INT(chn)); 934 writel(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), 935 priv->base + TSADCV3_HT_INT_EN); 936 } 937 938 static void tsadc_tshut_temp_v2(struct udevice *dev, 939 int chn, int temp) 940 { 941 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 942 struct chip_tsadc_table table = priv->data->table; 943 u32 tshut_value, val; 944 945 tshut_value = tsadc_temp_to_code_v2(table, temp); 946 if (tshut_value == table.data_mask) 947 return; 948 949 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 950 951 /* TSHUT will be valid */ 952 val = readl(priv->base + TSADCV2_AUTO_CON); 953 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 954 } 955 956 static void tsadc_tshut_temp_v3(struct udevice *dev, int chn, int temp) 957 { 958 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 959 struct chip_tsadc_table table = priv->data->table; 960 u32 tshut_value; 961 962 tshut_value = tsadc_temp_to_code_v2(table, temp); 963 if (tshut_value == table.data_mask) 964 return; 965 966 writel(tshut_value, priv->base + TSADCV3_COMP_SHUT(chn)); 967 writel(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), 968 priv->base + TSADCV3_AUTO_SRC_CON); 969 } 970 971 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 972 enum tshut_mode mode) 973 { 974 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 975 u32 val; 976 977 val = readl(priv->base + TSADCV2_INT_EN); 978 if (mode == TSHUT_MODE_GPIO) { 979 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 980 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 981 } else { 982 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 983 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 984 } 985 986 writel(val, priv->base + TSADCV2_INT_EN); 987 } 988 989 static void tsadc_tshut_mode_v4(struct udevice *dev, int chn, 990 enum tshut_mode mode) 991 { 992 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 993 u32 val_gpio, val_cru; 994 995 if (mode == TSHUT_MODE_GPIO) { 996 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 997 val_cru = TSADCV2_INT_SRC_EN_MASK(chn); 998 } else { 999 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1000 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); 1001 } 1002 writel(val_gpio, priv->base + TSADCV3_HSHUT_GPIO_INT_EN); 1003 writel(val_cru, priv->base + TSADCV3_HSHUT_CRU_INT_EN); 1004 } 1005 1006 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 1007 { 1008 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1009 1010 priv->data->tsadc_get_temp(dev, 0, temp); 1011 1012 return 0; 1013 } 1014 1015 static const struct dm_thermal_ops rockchip_thermal_ops = { 1016 .get_temp = rockchip_thermal_get_temp, 1017 }; 1018 1019 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = { 1020 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1021 .chn_num = 1, /* 1 channels for tsadc */ 1022 1023 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1024 .tshut_temp = 95000, 1025 1026 .tsadc_init = tsadc_init_v2, 1027 .tsadc_control = tsadc_control_v2, 1028 .tsadc_get_temp = tsadc_get_temp_v2, 1029 .irq_ack = tsadc_irq_ack_v3, 1030 .set_alarm_temp = tsadc_alarm_temp_v2, 1031 .set_tshut_temp = tsadc_tshut_temp_v2, 1032 .set_tshut_mode = tsadc_tshut_mode_v2, 1033 1034 .table = { 1035 .knum = 2699, 1036 .bnum = 2796, 1037 .data_mask = TSADCV2_DATA_MASK, 1038 .mode = ADC_INCREMENT, 1039 }, 1040 }; 1041 1042 static int rockchip_thermal_probe(struct udevice *dev) 1043 { 1044 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1045 struct rockchip_tsadc_chip *tsadc; 1046 struct clk clk; 1047 int ret, i, shut_temp; 1048 1049 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1050 ret = clk_set_defaults(dev); 1051 if (ret) 1052 printf("%s clk_set_defaults failed %d\n", __func__, ret); 1053 1054 if (soc_is_rk3308bs()) { 1055 ret = clk_get_by_name(dev, "tsadc", &clk); 1056 if (ret) { 1057 printf("%s get tsadc clk fail\n", __func__); 1058 return -EINVAL; 1059 } 1060 ret = clk_set_rate(&clk, 4000000); 1061 if (ret < 0) { 1062 printf("%s: failed to set tsadc clk rate for %s\n", 1063 __func__, dev_read_name(dev)); 1064 return -EINVAL; 1065 } 1066 1067 tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data; 1068 } else { 1069 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 1070 } 1071 priv->data = tsadc; 1072 1073 priv->tshut_mode = dev_read_u32_default(dev, 1074 "rockchip,hw-tshut-mode", 1075 -1); 1076 if (priv->tshut_mode < 0) 1077 priv->tshut_mode = priv->data->tshut_mode; 1078 1079 priv->tshut_polarity = dev_read_u32_default(dev, 1080 "rockchip,hw-tshut-polarity", 1081 -1); 1082 if (priv->tshut_polarity < 0) 1083 priv->tshut_polarity = tsadc->tshut_polarity; 1084 1085 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1086 pinctrl_select_state(dev, "otpout"); 1087 else 1088 pinctrl_select_state(dev, "gpio"); 1089 1090 tsadc->tsadc_init(dev); 1091 tsadc->irq_ack(dev); 1092 1093 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 1094 if (shut_temp < 0) 1095 shut_temp = 120000; 1096 1097 for (i = 0; i < tsadc->chn_num; i++) { 1098 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 1099 tsadc->set_tshut_temp(dev, i, shut_temp); 1100 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1101 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 1102 else 1103 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 1104 } 1105 1106 tsadc->tsadc_control(dev, true); 1107 if (soc_is_rk3308bs()) 1108 mdelay(3); 1109 else 1110 udelay(1000); 1111 1112 debug("tsadc probed successfully\n"); 1113 1114 return 0; 1115 } 1116 1117 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 1118 { 1119 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1120 1121 priv->base = dev_read_addr_ptr(dev); 1122 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1123 1124 return 0; 1125 } 1126 1127 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 1128 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1129 .chn_num = 1, /* one channel for tsadc */ 1130 1131 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1132 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1133 .tshut_temp = 95000, 1134 1135 .tsadc_init = tsadc_init_v2, 1136 .tsadc_control = tsadc_control_v3, 1137 .tsadc_get_temp = tsadc_get_temp_v2, 1138 .irq_ack = tsadc_irq_ack_v3, 1139 .set_alarm_temp = tsadc_alarm_temp_v2, 1140 .set_tshut_temp = tsadc_tshut_temp_v2, 1141 .set_tshut_mode = tsadc_tshut_mode_v2, 1142 1143 .table = { 1144 .id = rk1808_code_table, 1145 .length = ARRAY_SIZE(rk1808_code_table), 1146 .data_mask = TSADCV2_DATA_MASK, 1147 .mode = ADC_INCREMENT, 1148 }, 1149 }; 1150 1151 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 1152 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1153 .chn_num = 1, /* one channel for tsadc */ 1154 1155 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1156 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1157 .tshut_temp = 95000, 1158 1159 .tsadc_init = tsadc_init_v2, 1160 .tsadc_control = tsadc_control_v3, 1161 .tsadc_get_temp = tsadc_get_temp_v2, 1162 .irq_ack = tsadc_irq_ack_v3, 1163 .set_alarm_temp = tsadc_alarm_temp_v2, 1164 .set_tshut_temp = tsadc_tshut_temp_v2, 1165 .set_tshut_mode = tsadc_tshut_mode_v2, 1166 1167 .table = { 1168 .id = rk3228_code_table, 1169 .length = ARRAY_SIZE(rk3228_code_table), 1170 .data_mask = TSADCV3_DATA_MASK, 1171 .mode = ADC_INCREMENT, 1172 }, 1173 }; 1174 1175 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 1176 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 1177 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 1178 .chn_num = 2, /* two channels for tsadc */ 1179 1180 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1181 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1182 .tshut_temp = 95000, 1183 1184 .tsadc_init = tsadc_init_v2, 1185 .tsadc_control = tsadc_control_v2, 1186 .tsadc_get_temp = tsadc_get_temp_v3, 1187 .irq_ack = tsadc_irq_ack_v2, 1188 .set_alarm_temp = tsadc_alarm_temp_v2, 1189 .set_tshut_temp = tsadc_tshut_temp_v2, 1190 .set_tshut_mode = tsadc_tshut_mode_v2, 1191 1192 .table = { 1193 .id = rk3288_code_table, 1194 .length = ARRAY_SIZE(rk3288_code_table), 1195 .data_mask = TSADCV2_DATA_MASK, 1196 .mode = ADC_DECREMENT, 1197 }, 1198 }; 1199 1200 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 1201 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1202 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1203 .chn_num = 2, /* 2 channels for tsadc */ 1204 1205 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1206 .tshut_temp = 95000, 1207 1208 .tsadc_init = tsadc_init_v4, 1209 .tsadc_control = tsadc_control_v3, 1210 .tsadc_get_temp = tsadc_get_temp_v2, 1211 .irq_ack = tsadc_irq_ack_v3, 1212 .set_alarm_temp = tsadc_alarm_temp_v2, 1213 .set_tshut_temp = tsadc_tshut_temp_v2, 1214 .set_tshut_mode = tsadc_tshut_mode_v2, 1215 1216 .table = { 1217 .id = rk3328_code_table, 1218 .length = ARRAY_SIZE(rk3328_code_table), 1219 .data_mask = TSADCV2_DATA_MASK, 1220 .mode = ADC_INCREMENT, 1221 }, 1222 }; 1223 1224 static const struct rockchip_tsadc_chip px30_tsadc_data = { 1225 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1226 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1227 .chn_num = 2, /* 2 channels for tsadc */ 1228 1229 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1230 .tshut_temp = 95000, 1231 1232 .tsadc_init = tsadc_init_v4, 1233 .tsadc_control = tsadc_control_v3, 1234 .tsadc_get_temp = tsadc_get_temp_v2, 1235 .irq_ack = tsadc_irq_ack_v3, 1236 .set_alarm_temp = tsadc_alarm_temp_v2, 1237 .set_tshut_temp = tsadc_tshut_temp_v2, 1238 .set_tshut_mode = tsadc_tshut_mode_v2, 1239 1240 .table = { 1241 .id = rk3328_code_table, 1242 .length = ARRAY_SIZE(rk3328_code_table), 1243 .data_mask = TSADCV2_DATA_MASK, 1244 .mode = ADC_INCREMENT, 1245 }, 1246 }; 1247 1248 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 1249 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1250 .chn_num = 1, /* one channels for tsadc */ 1251 1252 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1253 .tshut_temp = 95000, 1254 1255 .tsadc_init = tsadc_init_v2, 1256 .tsadc_control = tsadc_control_v3, 1257 .tsadc_get_temp = tsadc_get_temp_v2, 1258 .irq_ack = tsadc_irq_ack_v3, 1259 .set_alarm_temp = tsadc_alarm_temp_v2, 1260 .set_tshut_temp = tsadc_tshut_temp_v2, 1261 .set_tshut_mode = tsadc_tshut_mode_v2, 1262 1263 .table = { 1264 .id = rk3328_code_table, 1265 .length = ARRAY_SIZE(rk3328_code_table), 1266 .data_mask = TSADCV2_DATA_MASK, 1267 .mode = ADC_INCREMENT, 1268 }, 1269 }; 1270 1271 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 1272 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1273 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1274 .chn_num = 2, /* two channels for tsadc */ 1275 1276 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1277 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1278 .tshut_temp = 95000, 1279 1280 .tsadc_init = tsadc_init_v3, 1281 .tsadc_control = tsadc_control_v3, 1282 .tsadc_get_temp = tsadc_get_temp_v2, 1283 .irq_ack = tsadc_irq_ack_v3, 1284 .set_alarm_temp = tsadc_alarm_temp_v2, 1285 .set_tshut_temp = tsadc_tshut_temp_v2, 1286 .set_tshut_mode = tsadc_tshut_mode_v2, 1287 1288 .table = { 1289 .id = rk3228_code_table, 1290 .length = ARRAY_SIZE(rk3228_code_table), 1291 .data_mask = TSADCV3_DATA_MASK, 1292 .mode = ADC_INCREMENT, 1293 }, 1294 }; 1295 1296 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1297 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1298 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1299 .chn_num = 2, /* two channels for tsadc */ 1300 1301 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1302 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1303 .tshut_temp = 95000, 1304 1305 .tsadc_init = tsadc_init_v2, 1306 .tsadc_control = tsadc_control_v2, 1307 .tsadc_get_temp = tsadc_get_temp_v2, 1308 .irq_ack = tsadc_irq_ack_v2, 1309 .set_alarm_temp = tsadc_alarm_temp_v2, 1310 .set_tshut_temp = tsadc_tshut_temp_v2, 1311 .set_tshut_mode = tsadc_tshut_mode_v2, 1312 1313 .table = { 1314 .id = rk3368_code_table, 1315 .length = ARRAY_SIZE(rk3368_code_table), 1316 .data_mask = TSADCV3_DATA_MASK, 1317 .mode = ADC_INCREMENT, 1318 }, 1319 }; 1320 1321 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1322 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1323 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1324 .chn_num = 2, /* two channels for tsadc */ 1325 1326 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1327 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1328 .tshut_temp = 95000, 1329 1330 .tsadc_init = tsadc_init_v3, 1331 .tsadc_control = tsadc_control_v3, 1332 .tsadc_get_temp = tsadc_get_temp_v2, 1333 .irq_ack = tsadc_irq_ack_v3, 1334 .set_alarm_temp = tsadc_alarm_temp_v2, 1335 .set_tshut_temp = tsadc_tshut_temp_v2, 1336 .set_tshut_mode = tsadc_tshut_mode_v2, 1337 1338 .table = { 1339 .id = rk3399_code_table, 1340 .length = ARRAY_SIZE(rk3399_code_table), 1341 .data_mask = TSADCV3_DATA_MASK, 1342 .mode = ADC_INCREMENT, 1343 }, 1344 }; 1345 1346 static const struct rockchip_tsadc_chip rk3568_tsadc_data = { 1347 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1348 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1349 .chn_num = 2, /* two channels for tsadc */ 1350 1351 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1352 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1353 .tshut_temp = 95000, 1354 1355 .tsadc_init = tsadc_init_v7, 1356 .tsadc_control = tsadc_control_v3, 1357 .tsadc_get_temp = tsadc_get_temp_v2, 1358 .irq_ack = tsadc_irq_ack_v3, 1359 .set_alarm_temp = tsadc_alarm_temp_v2, 1360 .set_tshut_temp = tsadc_tshut_temp_v2, 1361 .set_tshut_mode = tsadc_tshut_mode_v2, 1362 1363 .table = { 1364 .id = rk3568_code_table, 1365 .length = ARRAY_SIZE(rk3568_code_table), 1366 .data_mask = TSADCV2_DATA_MASK, 1367 .mode = ADC_INCREMENT, 1368 }, 1369 }; 1370 1371 static const struct rockchip_tsadc_chip rk3588_tsadc_data = { 1372 /* top, big_core0, big_core1, little_core, center, gpu, npu */ 1373 .chn_id = {0, 1, 2, 3, 4, 5, 6}, 1374 .chn_num = 7, /* seven channels for tsadc */ 1375 1376 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1377 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1378 .tshut_temp = 95000, 1379 1380 .tsadc_init = tsadc_init_v8, 1381 .tsadc_control = tsadc_control_v4, 1382 .tsadc_get_temp = tsadc_get_temp_v4, 1383 .irq_ack = tsadc_irq_ack_v4, 1384 .set_alarm_temp = tsadc_alarm_temp_v3, 1385 .set_tshut_temp = tsadc_tshut_temp_v3, 1386 .set_tshut_mode = tsadc_tshut_mode_v4, 1387 1388 .table = { 1389 .id = rk3588_code_table, 1390 .length = ARRAY_SIZE(rk3588_code_table), 1391 .data_mask = TSADCV4_DATA_MASK, 1392 .mode = ADC_INCREMENT, 1393 }, 1394 }; 1395 1396 static const struct udevice_id rockchip_thermal_match[] = { 1397 { 1398 .compatible = "rockchip,px30-tsadc", 1399 .data = (ulong)&px30_tsadc_data, 1400 }, 1401 { 1402 .compatible = "rockchip,rk1808-tsadc", 1403 .data = (ulong)&rk1808_tsadc_data, 1404 }, 1405 { 1406 .compatible = "rockchip,rk3228-tsadc", 1407 .data = (ulong)&rk3228_tsadc_data, 1408 }, 1409 { 1410 .compatible = "rockchip,rk3288-tsadc", 1411 .data = (ulong)&rk3288_tsadc_data, 1412 }, 1413 { 1414 .compatible = "rockchip,rk3308-tsadc", 1415 .data = (ulong)&rk3308_tsadc_data, 1416 }, 1417 { 1418 .compatible = "rockchip,rk3308bs-tsadc", 1419 .data = (ulong)&rk3308bs_tsadc_data, 1420 }, 1421 { 1422 .compatible = "rockchip,rk3328-tsadc", 1423 .data = (ulong)&rk3328_tsadc_data, 1424 }, 1425 { 1426 .compatible = "rockchip,rk3366-tsadc", 1427 .data = (ulong)&rk3366_tsadc_data, 1428 }, 1429 { 1430 .compatible = "rockchip,rk3368-tsadc", 1431 .data = (ulong)&rk3368_tsadc_data, 1432 }, 1433 { 1434 .compatible = "rockchip,rk3399-tsadc", 1435 .data = (ulong)&rk3399_tsadc_data, 1436 }, 1437 { 1438 .compatible = "rockchip,rk3568-tsadc", 1439 .data = (ulong)&rk3568_tsadc_data, 1440 }, 1441 { 1442 .compatible = "rockchip,rk3588-tsadc", 1443 .data = (ulong)&rk3588_tsadc_data, 1444 }, 1445 { /* end */ }, 1446 }; 1447 1448 U_BOOT_DRIVER(rockchip_thermal) = { 1449 .name = "rockchip_thermal", 1450 .id = UCLASS_THERMAL, 1451 .of_match = rockchip_thermal_match, 1452 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1453 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1454 .ops = &rockchip_thermal_ops, 1455 .probe = rockchip_thermal_probe, 1456 }; 1457